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HT37A706050403020

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HT37A70/60/50/40/30/20

8-ChannelMusicSynthesizerMCUTechnicalDocument

·ApplicationNote-HA0075EMCUResetandOscillatorCircuitsApplicationNoteFeatures

·Operatingvoltage:

·16-bittablereadinstructionsforanybank/pageread·Support16to28bidirectionalI/Olines

·Integrated2-chstereoor1-chmono16-bitDAC

3.6V~5.5V(HT37A70/60)3.3V~5.5V(HT37A50/40)2.4V~5.5V(HT37A30/20)

·Operatingfrequency:11.059MHz·OscillationmodesfortheOscillatorclock

converter

·IntegratedpowerAmplifier

·Integrated8-channel12-bitA/Dconverter·Eightchannelpolyphonicsynthesizer·Lowvoltagereset(Tolerance±10%)·ExternalinterruptINT·External2Timerclockinput·4or8touchswitchinput·ADPCMdecoder

·Bitmanipulationinstructions·63powerfulinstructions

·Allinstructionsin1or2machinecycles

fOSC:Crystal(11.059MHz)

1-pinRCoscillationtyp.11.059MHz

·Built-in8-bitMCU(HT-8)with320´8bitsRAM·Built-in32K´16-bitsto256K´16-bitsROMfor

program/datashared

·Eight-levelsubroutinenesting·Two8bittimerandone16bittimer·Watchdogtimer

·Power-downandWake-upfeaturesforpowersaving

operation

GeneralDescription

Thedeviceisan8-bithighperformanceRISCarchitec-turemicrocontrollerspecificallydesignedforvariousMusicandADPCMapplications.Itprovidesan8-bitMCUand8-channelWavetablesynthesizer.Ithasain-tegrated8-bitmicrocontrollerwhichcontrolsthesyn-thesizertogeneratethemelodybysettingthespecialregister.APower-downfunctionisincludedtoreducepowerconsumption.

SelectionTable

Mostfeaturesarecommontoalldevices,themainfeaturedistinguishingthemareProgramMemorycapacity,I/Ocount,A/Dresolution,DACoutput,R2Finputandpackagetypes.Thefollowingtablesummarizesthemainfeaturesofeachdevice.

PartNo.VDDChannelOSCProgramROM32K´16bit2.4V~5.5VHT37A30HT37A40HT37A50HT37A60HT37A703.3V~5.5V3.6V~5.5V6+211.059MHzK´16bit96K´16bit128K´16bit192K´16bit256K´16bit320´8bit20282828282ch-Stereo2ch-Stereo2ch-Stereo2ch-Stereo2ch-StereoÖÖÖÖÖ883.0V812-bit´883.3V828SOP,QFP,80LQFPRAMI/OD/APowerCR/FAMP¾4LVR2.2V/3.3V2.2V/3.3VADC¾¾PackageTypes20/28SOP28SOP,48SSOPHT37A20161ch-monoRev.1.001February17,2009

HT37A70/60/50/40/30/20BlockDiagramPinAssignmentRev.1.002February17,2009

HT37A70/60/50/40/30/20HT37A70/60

Chipsize:2325´5155(mm)2

*TheICsubstrateshouldbeconnectedtoVSSinthePCBlayoutartwork.

Rev.1.003February17,2009

HT37A70/60/50/40/30/20HT37A50/40

Chipsize:2325´4070(mm)2

*TheICsubstrateshouldbeconnectedtoVSSinthePCBlayoutartwork.

Rev.1.004February17,2009

HT37A70/60/50/40/30/20HT37A30

Chipsize:2360´3325(mm)2

*TheICsubstrateshouldbeconnectedtoVSSinthePCBlayoutartwork.

Rev.1.005February17,2009

HT37A70/60/50/40/30/20HT37A20

Chipsize:2230´2735(mm)2

*TheICsubstrateshouldbeconnectedtoVSSinthePCBlayoutartwork.

Rev.1.006February17,2009

HT37A70/60/50/40/30/20PadCoordinates

HT37A70/60

PadNo.123456710111213141516171819202122232425

HT37A50/40

PadNo.123456710111213141516171819202122232425

Rev.1.00

X-1012.900-1012.900-1012.900-1013.195-1013.195-1013.195-998.595-998.595-971.945-974.5-975.025-975.025-1057.200-954.200-822.375-715.426-608.475-480.425-373.474-266.525-112.350-9.35085.650188.650283.650

Y9.835-.165-188.165-358.060-458.060-558.060-665.310-769.915-870.5-1027.417-1143.945-1249.245-1822.435-1822.435-1848.470-1848.470-1848.470-1848.470-1848.470-1848.470-1886.400-1886.400-1886.400-1886.400-1886.400

PadNo.262728293031323334353637383940414243444547484950

X386.650481.650584.650745.620847.7451012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.900

Y-1886.400-1886.400-1886.400-1842.210-1850.450-1851.940-1748.940-1653.940-1550.940-1455.940-1352.940-1257.940-1154.940-1059.940-956.940-861.940-758.940-663.940-560.940-465.940-362.940-267.940-166.740-63.74031.260February17,2009

Y-531.665-630.665-729.665-9.560-999.560-1099.560-1206.810-1311.415-1412.145-1568.917-1685.445-1790.745-2363.935-2363.935-23.970-23.970-23.970-23.970-23.970-23.970-2427.900-2427.900-2427.900-2427.900-2427.900

PadNo.262728293031323334353637383940414243444547484950

X386.650481.650584.650745.620847.7451012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.9001012.900

Y-2427.900-2427.900-2427.900-2383.710-2391.950-2393.440-2290.440-2195.440-2092.440-1997.440-14.440-1799.440-1696.441-1601.440-1498.440-1403.440-1300.440-1205.440-1102.440-1007.440-904.440-809.440-708.240-605.240-510.240

Unit:mmUnit:mm

HT37A70/60/50/40/30/20HT37A30

PadNo.12345671011121314151617181920

HT37A20

PadNo.12345671011121314

X-957.220-966.120-966.120-966.120-966.120-966.120-966.120-9.415-9.415-9.415-962.015-7.840-534.220-427.120

Y1218.355956.015853.015758.015-580.625-679.625-785.055-931.730-1018.730-1105.730-1202.625-1180.218-1183.955-1188.955

PadNo.15161718192021222324252627

X-305.520966.120966.120966.120966.120966.120757.770662.770559.770-561.220-6.220-759.220-862.220

Y-1218.355813.375916.3751011.3751114.3751209.3751218.3551218.3551218.3551218.3551218.3551218.3551218.355

X-1031.100-1031.100-1031.100-1038.550-1038.550-1038.550-1016.795-1016.795-1028.020-1030.970-1031.100-1031.100-1075.000-972.400-840.575-733.626-626.675-498.625-391.674-284.725

Y306.920207.920102.485-69.700-156.700-243.700-336.210-442.465-537.520-688.142-804.670-909.970-1449.785-1449.785-1475.820-1475.820-1475.820-1475.820-1475.820-1475.820

PadNo.2122232425262728293031323334353637383940

X1031.3401031.3401031.3401031.3401031.3401031.3401031.3401031.3401031.3401031.3401031.3401031.340777.240674.240579.240476.240381.240280.190177.19082.190

Y405.950508.950603.950706.950801.950904.950999.9501102.9501197.9501300.9501395.9501498.9501513.7501513.7501513.7501513.7501513.7501513.7501513.7501513.750

Unit:mmUnit:mm

Rev.1.008February17,2009

HT37A70/60/50/40/30/20PadDescription

HT37A70,HT37A60,HT37A50,HT37A40PadNameVDDVDD_DACVDD_AMPVDD_ADCVSSVSS_DACVSS_AMPVSS_ADCPA0~PA4PA5/INTPA6/TMR0PA7/TMR1

I/O¾¾¾¾¾¾¾¾

Configuration

Option

¾¾¾¾¾¾¾¾

PositivedigitalpowersupplyPositiveDACcircuitpowersupplyPositivepowerAmp.powersupplyPositiveADCcircuitpowersupplyNegativedigitalpowersupply,groundNegativeDACpowersupply,groundNegativeAMPpowersupply,groundNegativeADCpowersupply,ground

Bidirectional8-bitinput/outputport.Eachpincanbeconfiguredasawake-upinputbyconfigurationoption.SoftwareinstructionsdetermineifthepinisaCMOSoutputorSchmittTriggerinput.Configurationoptionsdetermineifallpinsonthisporthavepull-highresistors.PinsPA5,PA6andPA7arepin-sharedwithINT,TMR0andTMR1,respectively.

Bidirectional8-bitinput/outputport.SoftwareinstructionsdetermineifthepinisaCMOSoutputorSchmittTriggerinput.Aconfigurationoptiondeterminesifallpinsonthisporthavepull-highresistors.PinsPB0~PB7arepin-sharedwithAD0andAD7,respectively.

Bi-directional4-bitI/Oport.SoftwareinstructionsdeterminedtheCMOSout-putorSchmitttriggerwithapull-highresistor(determinedbypull-highoption:byoption).

PinsPD0~PD3arepin-sharedwithCR/FOSCinputpinsRCOUT,RR,RCandCC.

RCOUT,RR,RCandCCcontrolpinforCR/FFunction.AudiorightchanneloutputAudioleftchanneloutputPowerAmp.outputpinsPowerAmp.inputpin

PowerAmp.voltagebiasreferencepin.SchmittTriggerresetinput,activelow

OSC1,OSC2areconnectedtoanexternalRCnetworkorexternalcrystal,determinedbyconfigurationoption,fortheinternalsystemclock.IftheRCsystemclockoptionisselected,pinOSC2canbeusedtomeasurethesys-temclockat1/8frequency.

Function

I/O

Pull-highWake-up

PB0/AD0~PB7/AD7

I/OPull-high

PC0/K0~PC7/K7

I/OPull-high

PD0/RCOUTPD1/RRPD2/RCPD3/CCRCHLCHSP1,SP0AUD_INVBIASRESOSC1OSC2

I/OPull-high

OOOIOIIO

¾¾¾¾¾¾

CrystalorRC

Note:1.EachpinonPAcanbeprogrammedthroughaconfigurationoptiontohaveawake-upfunction.2.Individualpinscanbeselectedtohavepull-highresistors.

3.BecausethetwotimersareusedbyMIDItheexternaltimerpinfunctionsaredisabled.

Rev.1.009February17,2009

HT37A70/60/50/40/30/20HT37A30PadNameVDDVDD_DACVDD_AMPVSSVSS_DACVSS_AMPPA0~PA4PA5/INTPA6/TMR0PA7/TMR1

I/O¾¾¾¾¾¾

Configuration

Option

¾¾¾¾¾¾

PositivedigitalpowersupplyPositiveDACcircuitpowersupplyPositivepowerAmp.powersupplyNegativedigitalpowersupply,groundNegativeDACpowersupply,groundNegativeAMPpowersupply,ground

Bi-directional4-bitI/Oport.SoftwareinstructionsdeterminedtheCMOSout-putorSchmitttriggerwithapull-highresistor(determinedbypull-highoption:byoption).

PinsPD0~PD3arepin-sharedwithCR/FOSCinputpinsRCOUT,RR,RCandCC.

RCOUT,RR,RCandCCcontrolpinforCR/FFunction.AudiorightchanneloutputAudioleftchanneloutputPowerAmp.outputpinsPowerAmp.inputpin

PowerAmp.voltagebiasreferencepin.SchmittTriggerresetinput,activelow

Function

I/O

Pull-highWake-up

PC0/K0~PC7/K7

I/OPull-high

PD0/RCOUTPD1/RRPD2/RCPD3/CCRCHLCHSP1,SP0AUD_INVBIASRESOSC1,OSC2

I/OPull-high

OOOIOIIO

¾¾¾¾¾¾

CrystalorRC

Note:1.EachpinonPAcanbeprogrammedthroughaconfigurationoptiontohaveawake-upfunction.2.Individualpinscanbeselectedtohavepull-highresistors.

3.BecausethetwotimersareusedbyMIDItheexternaltimerpinfunctionsaredisabled.

Rev.1.0010February17,2009

HT37A70/60/50/40/30/20HT37A20PadNameVDDVDD_DACVSSVSS_DACPA0~PA4PA5/INTPA6/TMR0PA7/TMR1

I/O¾¾¾¾

Configuration

Option

¾¾¾¾

PositivedigitalpowersupplyPositiveDACcircuitpowersupplyNegativedigitalpowersupply,groundNegativeDACpowersupply,ground

Bidirectional4-bitinput/outputport.SoftwareinstructionsdetermineifthepinisaCMOSoutputorSchmittTriggerinput.Aconfigurationoptiondeterminesifallpinsonthisporthavepull-highresistors.PinsPC0~PC3arepin-sharedwithK0andK3,respectively(K0~K3areCR/Ffunction).

Bi-directional4-bitI/Oport.SoftwareinstructionsdeterminedtheCMOSout-putorSchmitttriggerwithapull-highresistor(determinedbypull-highoption:byoption).

PinsPD0~PD3arepin-sharedwithCR/FOSCinputpinsRCOUT,RR,RCandCC.

RCOUT,RR,RCandCCcontrolpinforCR/FFunction.Audiorightchanneloutput

SchmittTriggerresetinput,activelow

Function

I/O

Pull-highWake-up

PC0/K0~PC3/K3

I/OPull-high

PD0/RCOUTPD1/RRPD2/RCPD3/CCRCHRESOSC1OSC2

I/OPull-high

OIIO

¾¾

CrystalorRC

Note:1.EachpinonPAcanbeprogrammedthroughaconfigurationoptiontohaveawake-upfunction.2.Individualpinscanbeselectedtohavepull-highresistors.

3.BecausethetwotimersareusedbyMIDItheexternaltimerpinfunctionsaredisabled.

AbsoluteMaximumRatings

SupplyVoltage..........................VSS-0.3VtoVSS+5.5VInputVoltage.............................VSS-0.3VtoVDD+0.3VIOLTotal..............................................................150mATotalPowerDissipation.....................................500mW

StorageTemperature...........................-50°Cto125°COperatingTemperature..........................-20°Cto70°CIOHTotal............................................................-100mA

Note:Thesearestressratingsonly.Stressesexceedingtherangespecifiedunder²AbsoluteMaximumRatings²may

causesubstantialdamagetothedevice.Functionaloperationofthisdeviceatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicereliability.

Rev.1.0011February17,2009

HT37A70/60/50/40/30/20D.C.Characteristics

Symbol

Parameter

TestConditionsVDD

Conditions

fOSC=11.059MHzforHT37A30/20

VDD

OperatingVoltage

fOSC=11.059MHzforHT37A50/40fOSC=11.059MHzforHT37A70/60

IDD

OperatingCurrent

(CrystalOSCorRCOSC)StandbyCurrent(WDTDisable)

3VNoload,

fOSC=8MHz~12.8MHz,5VDACdisable

3VNoload,systemHALT,5VWDTdisable

3VNoload,systemHALT,5VWDTenable¾¾¾¾3V5V3V5V3V5V

VOL=0.1VDDVOH=0.9VDD

¾¾

LVR2.2Voption

VLVRIOIADC

LowVoltageResetVoltageAUDCurrentSource

AdditionalPowerConsumptionifA/DConverterisUsed

5VLVR3.0Voption

LVR3.3Voption¾3V5V

VOH=0.9VDD

(THD+N)/S£1%,RL=8WVIN=1kHzSinewave(THD+N)/S£10%,RL=8WVIN=1kHzSinewave(THD+N)/S£1%,RL=8WVIN=1kHzSinewave(THD+N)/S£10%,RL=8WVIN=1kHzSinewave

¾¾¾¾

Min.2.43.33.6¾¾¾¾¾¾00.7VDD

00.9VDD

610-2-520102.02.73.0¾¾¾¾¾¾¾

Typ.3.04.54.528¾¾¾¾¾¾¾¾1225-4-860302.23.03.3-30.51.590125385490

Max.5.55.55.5816125100.3VDDVDD0.4VDDVDD¾¾¾¾100502.43.33.6¾13¾¾¾¾

Ta=25°CUnitVVVmAmAmAmAmAmAVVVVmAmAmAmAkWkWVVVmAmAmAmWmWmWmW

ISTB1ISTB2VIL1VIH1VIL2VIH2IOLIOHRPH

StandbyCurrent(WDTEnable)InputLowVoltageforI/OPortsInputHighVoltageforI/OPortsInputLowVoltage(RES)InputHighVoltage(RES)I/OPortSegmentLogicOutputSinkCurrent

I/OPortSegmentLogicOutputSourceCurrent

Pull-highResistanceofI/OPorts

InternalAMPOutputPower

Note:LVR3.0VonlyappliestoHT37A50andHT37A40.

Rev.1.0012February17,2009

HT37A70/60/50/40/30/20A.C.Characteristics

Symbol

Parameter

TestConditions

VDD¾3V5V¾¾¾

Conditions

2.4V~5.5V3.3V~5.5V3.6V~5.5V

¾¾¾

Power-uporwake-upfromHALT

Min.80008000800045321¾0.25

Typ.1105911059110599065¾10241.00

Max.128001280012800180130¾¾2.00

Ta=25°CUnitkHzkHzkHzmsmsmstSYSms

fOSC

OscillatorClock

(CrystalOSC/RCOSC)

tWDTOSCtREStSSTtLVRNote:

WatchdogOscillatorPeriodExternalResetLowPulseWidthSystemStart-upTimerPeriodLowVoltageWidthtoResettSYS=1/fSYSfSYS=fOSC/2

CharacteristicsCurves

Rev.1.0013February17,2009

HT37A70/60/50/40/30/20(THD+N)vs.OutputPower

RLOAD=8W,VIN=1kHzSinewavefor3.0V

RLOAD=8W,VIN=1kHzSinewavefor5.0V

Rev.1.0014February17,2009

HT37A70/60/50/40/30/20SystemArchitecture

Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofMusicTypemicrocontrollersisattrib-utedtotheinternalsystemarchitecture.TherangeofdevicestakeadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstructionexecutionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withtheexceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyalloperationsofthein-structionset.Itcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchde-cisions,etc.Theinternaldatapathissimplifiedbymov-ingdatathroughtheAccumulatorandtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectlyorindirectlyaddressed.Thesimpleaddressingmethodsoftheseregistersalongwithaddi-tionalarchitecturalfeaturesensurethataminimumofexternalcomponentsisrequiredtoprovideafunctionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.

ClockingandPipelining

Themainsystemclock,derivedfromeitheraCrys-tal/ResonatororRCoscillator.Theoscillatorfrequencydividedby2issubdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedatthebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsone

instructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncy-cles,thepipeliningstructureofthemicrocontrolleren-suresthatinstructionsareeffectivelyexecutedinoneinstructioncycle.TheexceptiontothisareinstructionswherethecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.WhentheRCoscillatorisused,OSC2isfreedforuseasaT1phaseclocksynchronizingpin.ThisT1phaseclockhasafrequencyoffOSC/8witha1:3high/lowdutycycle.Forinstructionsinvolvingbranches,suchasjumporcallinstructions,twomachinecyclesarerequiredtocompleteinstructionexecution.Anextracycleisrequiredastheprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbypro-grammersintimingsensitiveapplications.ProgramCounter

Duringprogramexecution,theProgramCounterisusedtokeeptrackoftheaddressofthenextinstructiontobeexecuted.Itisautomaticallyincrementedbyoneeachtimeaninstructionisexecutedexceptforinstructions,suchas²JMP²or²CALL²,thatdemandajumptoanon-consecutiveProgramMemoryaddress.NotethattheProgramCounterwidthvarieswiththeProgramMemorycapacitydependinguponwhichdeviceisse-lected.However,itmustbenotedthatonlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebyuser.

SystemClockingandPipelining

InstructionFetching

Rev.1.0015February17,2009

HT37A70/60/50/40/30/20Whenexecutinginstructionsrequiringjumpstonon-consecutiveaddressessuchasajumpinstruction,asubroutinecall,interruptorreset,etc.,themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forcondi-tionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdis-cardedandadummycycletakesitsplacewhilethecor-rectinstructionisobtained.

ThelowerbyteoftheProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwritableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly,however,asonlythislowbyteisavailableformanipulation,thejumpsarelimitedtothepresentpageofmemory,thatis256locations.Whensuchprogramjumpsareexecuteditshouldalsobenotedthatadummycyclewillbein-serted.

ThelowerbyteoftheProgramCounterisfullyaccessi-bleunderprogramcontrol.ManipulatingthePCLmightcauseprogrambranching,soanextracycleisneededtopre-fetch.FurtherinformationonthePCLregistercanbefoundintheSpecialFunctionRegistersection.Stack

ThisisaspecialpartofthememorywhichisusedtosavethecontentsoftheProgramCounteronly.Thestackcanhave8levelsdependinguponwhichoptionisselectedandisneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwritable.TheactivatedlevelisindexedbytheStackPointer,SP,andisneitherreadablenorwritable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsofthePro-gramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisre-storedtoitspreviousvaluefromthestack.Afterade-vicereset,theStackPointerwillpointtothetopofthestack.

ProgramCounter

b17~b13000000000000000000000000000000

b12b11b10000000

000000

b9000000

b8000000

b7000000

b6000000

b5000000

b4000111

b3011001

b2001010

b1000000

b0000000

Mode

InitialReset

Timer/EventCounter0Overflow

Timer/EventCounter1OverflowTimerCounter2OverflowERCOCIInterruptADPCMInterruptSkipLoadingPCLJump,CallBranchReturnfromSubroutine

ProgramCounter+2(WithinCurrentBank)

P17~P13

P12P11P10

P9#9S9

P8#8S8

@7#7S7

@6#6S6

@5#5S5

@4#4S4

@3#3S3

@2#2S2

@1#1S1

@0#0S0

BP1.4~BP1.0#12#11#10S17~S13

S12S11S10

ProgramCounter

Note:

P17~P8:ProgramCounterbits@7~@0:PCLbits

#12~#0:InstructioncodeaddressbitsBP1.4~BP1.0:ROMbankpointerS17~S0:Stackregisterbits

FortheHT37A70/60,theProgramCounteris18bitswide,i.e.fromb17~b0.

FortheHT37A50/40,theProgramCounteris17bitswide,i.e.fromb16~b0,thereforetheb17columninthetableisnotapplicable.

FortheHT37A30,theProgramCounteris16bitswide,i.e.fromb15~b0,thereforetheb17andb16thecol-umnsinthetablearenotapplicable.

FortheHT37A20,theProgramCounteris15bitswide,i.e.fromb14~b0,thereforetheb17,b16andb15thecolumnsinthetablearenotapplicable.

Rev.1.0016February17,2009

HT37A70/60/50/40/30/2016bitsdependinguponwhichdeviceisselected.TheProgramMemoryisaddressedbytheProgramCounterandROMbankpoint,andalsocontainsgeneraldata,Wavetabledata,tableinformationandinterruptentries.Tabledata,whichcanbesetupinanylocationwithintheProgramMemory,isaddressedbyseparatetablepointerregisters.SpecialVectors

WithintheProgramMemory,certainlocationsarere-servedforspecialusagesuchasresetandinterrupts.

·Location000H

Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheac-knowledgesignalwillbeinhibited.WhentheStackPointerisdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowal-lowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutinein-structioncanstillbeexecutedwhichwillresultinastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.

ArithmeticandLogicUnit-ALU

Thearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicop-erationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedin-structioncodesandperformstherequiredarithmeticorlogicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroper-ationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyup-datedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:

·Arithmeticoperations:ADD,ADDM,ADC,ADCM,

Thisvectorisreservedforusebythedeviceresetforprograminitialization.Afteradeviceresetisinitiated,theprogramwilljumptothislocationandbeginexecu-tion.

·Location004H

Thisvectorisusedbytheexternalinterrupt.Iftheex-ternalinterruptpinonthedevicegoeslow,thepro-gramwilljumptothislocationandbeginexecutioniftheexternalinterruptisenabledandthestackisnotfull.

·Location008H

ThisvectorisreservedfortheTimer/EventCounter0interruptserviceprogram.IfatimerinterruptresultsfromaTimer/EventCounter0overflow,andifthein-terruptisenabledandthestackisnotfull,theprogrambeginsexecutionatlocation008H.

·Location00CH

ThisvectorisreservedfortheTimer/EventCounter1interruptserviceprogram.IfatimerinterruptresultsfromaTimer/EventCounter1overflow,andifthein-terruptisenabledandthestackisnotfull,theprogrambeginsexecutionatlocation00CH.

·Location010H

SUB,SUBM,SBC,SBCM,DAA

·Logicoperations:AND,OR,XOR,ANDM,ORM,

XORM,CPL,CPLA

·RotationRRA,RR,RRCA,RRC,RLA,RL,RLCA,

ThisvectorisreservedfortheTimerCounter2inter-ruptserviceprogram.IfatimerinterruptresultsfromaTimerCounter2overflow,andiftheinterruptisen-abledandthestackisnotfull,theprogrambeginsex-ecutionatlocation0010H.

·Location014H

RLC

·IncrementandDecrementINCA,INC,DECA,DEC·Branchdecision,JMP,SZ,SZA,SNZ,SIZ,SDZ,

SIZA,SDZA,CALL,RET,RETI

ProgramMemory

TheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ThetypeofmemoryisthemaskROMmemory.Itofferthemostcosteffectivesolu-tionsforhighvolumeproducts.Structure

TheProgramMemoryhasacapacityof256Kby16,192Kby16,128Kby16,96Kby16,Kby16or32Kby

ThisvectorisreservedfortheERCOCIinterruptser-viceprogram.IfanexternalRCoscillationconverterinterruptresultsfromanexternalRCoscillationcon-verterinterruptisactivated,andthestackisnotfull,theprogrambeginsexecutionatlocation0014H.

·Location018H

ThisvectorisreservedfortheAdpcminterruptserviceprogram.IfaAdpcminterruptresults,andiftheinter-ruptisenabledandthestackisnotfull,theprogrambeginsexecutionatlocation0018H.

Rev.1.0017February17,2009

HT37A70/60/50/40/30/20ProgramMemoryStructure

Rev.1.0018February17,2009

HT37A70/60/50/40/30/20Look-upTable

AnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressofthelookupdatatoberetrievedinthethreetablepointerregisters,TBLP,TBMPandTBHP.Thisthreeregistersdefinethead-dressofthelook-uptable.Aftersettingupthetablepointer,thetabledatacanberetrievedfromthecurrentProgramMemoryorlastProgramMemorypageinthespecificbankwhichdefinedbybankpointregisterasBP1usingthe²TABRDC[m]²or²TABRDL[m]²instruc-tions,respectively.Whentheseinstructionsareexe-cuted,thelowerordertablebytefromtheProgramMemorywillbetransferredtotheuserdefinedDataMemoryregister[m]asspecifiedintheinstruction.ThehigherordertabledatabytefromtheProgramMemorywillbetransferredtotheTBLHspecialregister.Anyun-usedbitsinthistransferredhigherorderbytewillhaveuncertainvalues.

Thefollowingdiagramillustratestheaddressing/dataflowofthelook-uptable:

TableProgramExample

ThefollowingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromtheHT37A70/60/50/30/40/20microcontroller.ThisexampleusesrawtabledatalocatedinthelastpageofROMBank1whichisstoredthereusingtheORGandROMbankstatement.ThelocationatprogramROM²3F00H²whichreferstothestartaddressofthelastpagewithintheProgramMemoryoftheHT37A70/60/50/40/30/20microcontroller.Thetablepointerissetupheretohaveaninitialvalueof²06H².Thiswillensurethatthefirstdatareadfromthedatata-blewillbeattheProgramMemoryaddress²3F06H²or6locationsafterthestartofthelastpageinselectedROMbank.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHreg-isterautomaticallywhenthe²TABRDL[m]²instructionisexecuted.BecausetheTBLHregisterisaread-onlyreg-isterandcannotberestored,careshouldbetakentoen-sureitsprotectionifboththemainroutineandInterruptServiceRoutineusetablereadinstructions.Ifusingthetablereadinstructions,theInterruptServiceRoutinesmaychangethevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitisrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However,insitua-tionswheresimultaneoususecannotbeavoided,thein-terruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.

Instruction

TableLocationBits

b17~b13BP1_4~BP1_0

b12~b811111

b7@7

b6@6@6

b5@5@5

b4@4@4

b3@3@3

b2@2@2

b1@1@1

b0@0@0

TABRDC[m]TBHP1_1~TBMP1_5TBMP1_4~TBMP1_0@7TABRDL[m]

TableLocation

Note:

@7~@0:Tablepointerlower-orderbitsareTBLP1[7:0]b17~b0:CurrentprogramROMtableaddressA[17:0]TBMP1_4~TBMP1_0:TBMP1bit4~0

TBHP1_1~TBMP1_5:TBHP1(bit1~0)toTBMP1(bit7~5)BP1_4~BP1_0:BitsofbankBP1bit0~4

FortheHT37A70/60,theTableaddresslocationis18bitswide,i.e.fromb17~b0.FortheHT37A50/40,theTableaddresslocationis17bitswide,i.e.fromb16~b0.FortheHT37A30,theTableaddresslocationis16bitswide,i.e.fromb15~b0.FortheHT37A20,theTableaddresslocationis15bitswide,i.e.fromb14~b0.

Rev.1.0019February17,2009

HT37A70/60/50/40/30/20tempreg1tempreg2tempreg3tempreg4movmovmovmovclrclr

dbdbdbdb

????

;;;;

temporarytemporarytemporarytemporary

registerregisterregisterregister

#1#2#3#4

a,01hbp1,aa,06htblp1,atbmpltbhpl::

;setROMbank1point;initialisetablepointer;tothelastpage

tabrdltempreg1

;;;;transfersvalueintablereferencedbytablepointertotempregl

dataatprog.memoryaddress²3F06H²transferredtotempreg1andTBLH

dectblp1tabrdl

tempreg2

;reducevalueoftablepointerbyone;;;;;;;;

transfersvalueintablereferencedbytablepointertotempreg2

dataatprog.memoryaddress²3F05H²transferredtotempreg2andTBLH

inthisexamplethedata²1AH²istransferredtotempreg1anddata²0FH²toregistertempreg2

thevalue²00H²willbetransferredtothehighbyteregisterTBLH

::mova,04hmovtblp1,amova,3Fhmovtbmp1,amova,00h

movtbhp1,atabrdctempreg3::

;initialisetablepointerlowbyte;

;initialisetablepointermiddlebyte;initialisetablepointerhighbyte;

rombank1romsumvalue1;setsrombank1initialaddressoflastpage

;(forHT37A70/60/50/40/30/20)romsumvalue1.sectionat1F00h¢code¢dc

00Ah,00Bh,00Ch,00Dh,00Eh,00Fh,01Ah,01Bh::

Rev.1.0020February17,2009

HT37A70/60/50/40/30/20ROMBankPointer(2DH)

Theprogrammemoryisorganizedinto32/24/16/12/8/4banksforHT37A70/60/50/40/30/20andeachbankinto8192´16bitsofprogramROM.BP1.7~BP1.0isusedasthebankpointer.AfteraninstructionhasbeenexecutedtowritedatatotheBP1registertoselectadifferentbank,notethatthenewbankwillnotbeselectedimmediately.Itisuntiltheinstruction²JMP²or²CALL²orinterrupthascompletedexecutionthatthebankwillbeactuallyselected.Register

BitNo.

Function

00000000b=SelectROMBank0(0000h~1FFFh)00000001b=SelectROMBank1(2000h~3FFFh)00000010b=SelectROMBank2(4000h~5FFFh)00000011b=SelectROMBank3(6000h~7FFFh)

00011110b=SelectROMBank30(3C000h~3DFFFh)00011111b=SelectROMBank31(3E000h~3FFFFh)

BP1(2DH)0~7

Note:FortheHT37A70/60,theROMbankpointregisteris5bitswideeffectively,i.e.fromb4~b0.FortheHT37A50/40,theROMbankpointregisteris4bitswideeffectively,i.e.fromb3~b0.FortheHT37A30,theROMbankpointregisteris3bitswideeffectively,i.e.fromb2~b0.FortheHT37A20,theROMbankpointregisteris2bitswideeffectively,i.e.fromb1~b0.

RAMDataMemory

TheRAMDataMemoryisavolatileareaof8-bitwideRAMinternalmemoryandisthelocationwheretempo-raryinformationisstored.Dividedintotwosections,thefirstoftheseisanareaofRAMwherespecialfunctionregistersarelocated.Theseregistershavefixedloca-tionsandarenecessaryforcorrectoperationofthede-vice.

Manyoftheseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,someremainprotectedfromusermanipulation.ThesecondareaofRAMDataMemoryisreservedforgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessi-bleunderprogramcontrol.

commontoallmicrocontrollers,suchasACC,PCL,etc.,havethesameDataMemoryaddress.Bank1oftheRAMDataMemoryislocatedataddress²60H².TheRAMdatamemoryisdesignedwith320´8bitswith2RAMbanks.TherearetwoRAMBANKpointers(RBP1andRBP2)controlBank0~1(RBP1.0/RBP2.0)Thedatamemoryisdesignedwith256bytesanddi-videdintofivefunctionalgroups:specialfunctionregis-ters(00H~1FH),musicsynthesiscontrollerregisters(20H~2FH),ADPCMdecodercontrollerregister(30H~35H),theotherfunction(35H~5FH)andgeneralpurposedatamemory(60H~FFH).

TheyarealsoindirectlyaccessiblethroughMemorypointerregistersMP0,MP1andMP2,whereMP1/MP2candealwithallbanksofdatamemorybutMP0dealwithBank0datamemoryonly.RBP1(04H)bit0controlMP1RBP2(2FH)bit0controlMP2GeneralPurposeDataMemory

Allmicrocontrollerprogramsrequireanareaofread/writememorywheretemporarydatacanbestoredandretrievedforuselater.ItisthisareaofRAMmemorythatisknownasGeneralPurposeDataMemory.ThisareaofDataMemoryisfullyaccessiblebytheuserpro-gramforbothreadandwriteoperations.Thebank0datamemoryareascanhandlearithmetic,logic,incre-ment,decrementandrotateoperationsdirectly.Byus-ingthe²SET[m].i²and²CLR[m].i²instructionsindividualbitscanbesetorresetunderprogramcontrolgivingtheuseralargerangeofflexibilityforbitmanipu-lationintheDataMemory.

Bank0~Bank1RAMDataMemoryStructureStructure

TheRAMDataMemoryissubdividedinto2banks,knownasBank0andBank1,allofwhichareimple-mentedin8-bitwideRAM.MostoftheRAMDataMem-oryislocatedinBank0whichisalsosubdividedintotwosections,theSpecialPurposeDataMemoryandtheGeneralPurposeDataMemory.ThestartaddressoftheDataMemoryistheaddress²00H².Registerswhichare

Rev.1.0021February17,2009

HT37A70/60/50/40/30/20SpecialPurposeDataMemory

ThisareaofDataMemoryiswhereregisters,necessaryforthecorrectoperationofthemicrocontroller,arestored.suchastimers,interrupts,etc.,aswellasexter-nalfunctionssuchasI/OdatacontrolandA/Dconverteroperation.Mostoftheregistersarebothreadableandwritablebutsomeareprotectedandarereadableonly,

thedetailsofwhicharelocatedundertherelevantSpe-cialFunctionRegistersection.Notethatforlocationsthatareunused,anyreadinstructiontotheseaddresseswillreturnthevalue²00H².AlthoughtheSpecialPur-poseDataMemoryregistersarelocatedinBank0,theywillstillbeaccessibleeveniftheBankPointerhasse-lectedBank1.

DataMemoryStructure

Rev.1.0022February17,2009

HT37A70/60/50/40/30/20SpecialFunctionRegisters

Toensuresuccessfuloperationofthemicrocontroller,certaininternalregistersareimplementedintheRAMDataMemoryarea.Theseregistersensurecorrectop-erationofinternalfunctionssuchastimers,interrupts,watchdog,etc.,aswellasexternalfunctionssuchasI/Odatacontrol.ThelocationoftheseregisterswithintheRAMDataMemorybeginsattheaddress²00H².IndirectAddressingRegister-IAR0,IAR1

TheIndirectAddressingRegisters,IAR0andIAR1,al-thoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregis-ters.ThemethodofindirectaddressingforRAMdatamanipulationusestheseIndirectAddressingRegistersandMemoryPointers,incontrasttodirectmemoryad-dressing,wheretheactualmemoryaddressisspeci-fied.ActionsontheIAR0andIAR1registerswillresultinnoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorre-spondingMemoryPointer,MP0orMP1/MP2.Actingasapair,IAR0andMP0cantogetheronlyaccessdatafromBank0,whiletheIAR1andMP1/MP2registercanExample

ThefollowingexampleshowshowtoclearGeneralPurposeDataMemoryofbank0byusingMP0andbank0~bank1byusingMP1andMP2

code.sectionat0codeorg00hRAM0TEST:

MOVA,60HMOVMP0,A;loadedwithfirstRAMaddressLOOP0:

CLRIAR0;clearthedataataddressdefinedbyMP0CLRWDTSIZMP0;increaseMP0,andskipoutifMP0is²0²JMPLOOP0:

RAM1TEST:

CLRDACC.7;accessdatatoiar1byMP1CLRrBP1;clearRAMbankpointer1RAM1_MP1:

MOVA,rBP1;loadrBP1data,andcheckifrBP1is²25²XORA,25SZZERO;jumptoexitloopifrBP1is²2²JMPRAM1TEST_ExitMOVA,60H;loadedwithfirstRAMaddresstoMP1MOVMP1,ALOOP1:

CLRWDTCLRIAR1;clearthedataataddressdefinedbyMP1SIZMP1;increaseMP1,andskipoutifMP1is²0²JMPLOOP1INCrBP1;increaserBP1JMPRAM1_MP1RAM1TEST_Exit:

RAM2TEST:

Setdacc.7;accessdatatoiar1byMP2CLRrBP2;clearRAMbankpointer2

accessdatafrombothBank0andBank1.UsingMP1or

MP2areselectedbyDACC.7.AstheIndirectAd-dressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof²00H²andwritingtotheregistersindi-rectlywillresultinnooperation.MemoryPointer-MP0,MP1,MP2

ThreeMemoryPointers,knownasMP0,MP1andMP2areprovided.TheseMemoryPointersarephysicallyim-plementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconve-nientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegis-tersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedto,istheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister,IAR0,areusedtoaccessdatafromBank0only,whileMP1/MP2andIAR1areusedtoaccessdatafrombothBank0andBank1.UsingMP1orMP2areselectedbyDACC.7.

Rev.1.0023February17,2009

HT37A70/60/50/40/30/20RAM1MP2:

MOVA,RBP2XORA,25SZZERO

JMPRAM2TEST_ExitMOVA,60HMOVMP2,ALOOP2:

CLRWDTCLRIAR1SIZMP2JMPLOOP2INCrBP2JMPRAM1MP2RAM2TEST_Exit:

:BankPointer-RBP1,RBP2

TheRAMDataMemoryisdividedinto2Banks,knownasBank0toBank1.SelectingtherequiredDataMemoryareaisachievedusingtheRAMBankPointerswhichareRBP1andRBP2.TheRBP1andRBP2matchupwithMP1andMP2respectively.IfdatainBank0istobeac-cessed,thentheRBPregistersmustbeloadedwiththevalue²00²,whileifdatainBank1istobeaccessed,thentheRBPregistersmustbeloadedwiththevalue²01².UsingMemoryPointerMP0andIndirectAddressingRegisterIAR0willalwaysaccessdatafromBank0,irre-spectiveofthevalueoftheBankPointer.TheRBP1andRBP2registerislocatedatmemorylocation60HinBank0toBank1andcanonlybeaccessedindirectlyusingtwomemorypointersMP1andMP2andtheindi-rectaddressingregisterIAR1willalwaysaccessdatafromBank0toBank1.

TheDataMemoryisinitializedtoBank0toBank1afterareset,exceptfortheWDTtime-outresetinthePowerDownMode,inwhichcase,theDataMemorybankre-mainsunaffected.ItshouldbenotedthatSpecialFunc-tionDataMemoryisnotaffectedbythebankselection,whichmeansthattheSpecialFunctionRegisterscanbeaccessedfromwithinBank0toBank1.Directlyad-dressingtheDataMemorywillalwaysresultinBank0beingaccessedirrespectiveofthevalueoftheBankPointer.Register

BitNo.01~7

Function

RAMBankPoint1Select0=SelectRAMBank01=SelectRAMBank1UnusedbitRBP1(04H)

BitNo.01~7

Function

RAMBankPoint2Select0=SelectRAMBank01=SelectRAMBank1Unusedbit

Look-upTableRegisters-TBLP1,TBMP1,TBHP1,TBLH

Thesesevenspecialfunctionregistersareusedtocon-troloperationofthelook-uptablewhichisstoredintheProgramMemory.TBLP1,TBMP1andTBHP1arethetablepointerandindicatethelocationwherethetabledataislocated.Theirvaluemustbesetupbeforeanyta-blereadcommandsareexecuted.Theirvaluecanbechanged,forexampleusingthe²INC²or²DEC²instruc-tions,allowingforeasytabledatapointingandreading.TBLHisthelocationwherethehighorderbyteoftheta-bledataisstoredafteratablereaddatainstructionhasbeenexecuted.Notethatthelowerordertabledatabyteistransferredtoauserdefinedlocation.24

February17,2009

;jumptoexitloopifrBP2is²2²;loadedwithfirstRAMaddresstoMP2

;clearthedataataddressdefinedbyMP2;increaseMP2,andskipoutifMP2is²0²;increaserBP2

Accumulator-ACC

TheAccumulatoriscentraltotheoperationofanymicrocontrollerandiscloselyrelatedwithoperationscarriedoutbytheALU.TheAccumulatoristheplacewhereallintermediateresultsfromtheALUarestored.WithouttheAccumulatoritwouldbenecessarytowritetheresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc.,totheDataMemoryresultinginhigherprogrammingandtimingoverheads.DatatransferoperationsusuallyinvolvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuserdefinedregisterandanother,itisnecessarytodothisbypassingthedatathroughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.

ProgramCounterLowRegister-PCL

Toprovideadditionalprogramcontrolfunctions,thelowbyteoftheProgramCounterismadeaccessibletopro-grammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimple-mented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylo-cation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypageareper-mitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.

RBP1

RBP2

RBP2(2FH)

Note:UsingMP1orMP2areselectedbyDACC.7.

Rev.1.00

HT37A70/60/50/40/30/20WatchdogTimerRegister-WDTS

TheWatchdogfeatureofthemicrocontrollerprovidesanautomaticresetfunctiongivingthemicrocontrollerameansofprotectionagainstspuriousjumpstoincorrectProgramMemoryaddresses.Toimplementthis,atimerisprovidedwithinthemicrocontrollerwhichwillissuearesetcommandwhenitsvalueoverflows.ToprovidevariableWatchdogTimerresettimes,theWatchdogTimerclocksourcecanbedividedbyvariousdivisionra-tios,thevalueofwhichissetusingtheWDTSregister.Bywritingdirectlytothisregister,theappropriatedivi-sionratiofortheWatchdogTimerclocksourcecanbesetup.Notethatonlythelower3bitsareusedtosetdivi-sionratiosbetween1and128.StatusRegister-STATUS

This8-bitregistercontainsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanage-mentflagsareusedtorecordthestatusandoperationofthemicrocontroller.

WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,opera-tionsrelatedtothestatusregistermaygivedifferentre-sultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe²CLRWDT²or²HALT²in-struction.ThePDFflagisaffectedonlybyexecutingthe²HALT²or²CLRWDT²instructionorduringasystempower-up.

TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.

·Cissetifanoperationresultsinacarryduringanad-·ACissetifanoperationresultsinacarryoutofthe

lownibblesinaddition,ornoborrowfromthehighnib-bleintothelownibbleinsubtraction;otherwiseACiscleared.

·Zissetiftheresultofanarithmeticorlogicaloperation

iszero;otherwiseZiscleared.

·OVissetifanoperationresultsinacarryintothehigh-

est-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.

·PDFisclearedbyasystempower-uporexecutingthe

²CLRWDT²instruction.PDFissetbyexecutingthe²HALT²instruction.

·TOisclearedbyasystempower-uporexecutingthe

²CLRWDT²or²HALT²instruction.TOissetbyaWDTtime-out.

Inaddition,onenteringaninterruptsequenceorexecut-ingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.

InterruptControlRegisters-INTC,INTCH

Thetwo8-bitregisters,knownastheINTCandINTCHregisterwhichcontroltheoperationofbothexternalandinternaltimer,CR/FandADPCMinterrupts,andByset-tingvariousbitswithinthisregisterusingstandardbitmanipulationinstructions,theenable/disablefunctionoftheexternalandtimer,CR/FandADPCMinterruptscanbeindependentlycontrolled.Amasterinterruptbitwithinthisregister,theEMIbit,actslikeaglobalenable/dis-ableandisusedtosetalloftheinterruptenablebitsonoroff.Thisbitisclearedwhenaninterruptroutineisen-teredtodisablefurtherinterruptandissetbyexecutingthe²RETI²instruction.Note:

Insituationswhereotherinterruptsmayrequireservicingwithinpresentinterruptservicerou-tines,theEMIbitcanbemanuallysetbytheprogramafterthepresentinterruptservicerou-tinehasbeenentered.

ditionoperationorifaborrowdoesnottakeplacedur-ingasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.

StatusRegister

Rev.1.0025February17,2009

HT37A70/60/50/40/30/20Timer/EventCounterRegisters-TMR0H,TMR0L,TMR1L,TMR2L,TMR0C,TMR1C,TMR2C

HT37A70/60/50/40/30/20containstwo8-bitanda16-bitTimer/EventCounterswhichhasanassociatedregisterknownasTMR0HandTMR0L.arethelocationwherethetimer¢s16-bitvalueislocated.TMR1LandTMR2Larethelocationwherethetimer¢s8-bitvalueislocated.Anassociatedcontrolregister,knownasTMR0C,TMR1CandTMR2Ccontainsthesetupinformationforthetimer.

Input/OutputPortsandControlRegisters-PA,PB,PC,PD,PAC,PBC,PCC,PDC

WithintheareaofSpecialFunctionRegisters,theI/Oregistersandtheirassociatedcontrolregistersplayaprominentrole.AllI/OportshaveadesignatedregistercorrespondinglylabeledasPA,PB,PCandPD.TheselabeledI/OregistersaremappedtospecificaddresseswithintheDataMemoryasshownintheDataMemorytable,whichareusedtotransfertheappropriateoutputorinputdataonthatport.witheachI/OportthereisanassociatedcontrolregisterlabeledPAC,PBC,PCCandPDC,alsomappedtospecificaddresseswiththeDataMemory.Thecontrolregisterspecifieswhichpinsofthatportaresetasinputsandwhicharesetasoutputs.Tosetupapinasaninput,thecorrespondingbitofthecon-trolregistermustbesethigh,foranoutputitmustbesetlow.Duringprograminitialization,itisimportanttofirstsetupthecontrolregisterstospecifywhichpinsareout-putsandwhichareinputsbeforereadingdatafromorwritingdatatotheI/Oports.Oneflexiblefeatureoftheseregistersistheabilitytodirectlyprogramsinglebitsus-ingthe²SET[m].i²and²CLR[m].i²instructions.TheabilitytochangeI/OpinsfromoutputtoinputandviceversabymanipulatingspecificbitsoftheI/Ocontrolreg-istersduringnormalprogramoperationisausefulfea-tureofthesedevices.

D/AConverterRegisters-DAH,DAL,DACCHT37A70/60/50/40/30providetwo16-bitD/Aconvert-ers,whichcanselectstereoormonooutput.HT37A20onlysupportsone16-bitD/Aconverter,whichusemonooutput.ThecorrectoperationoftheD/Arequirestheuseoftwodataregisters,andacontrolregister.Itcontaina16-bitD/Aconverter,therearetwodataregisters,ahighbytedataregisterknownasDAH,andalowbytedataregisterknownasDAL.Thesearetheregisterlocationswherethedigitalvalueisplacedbeforethecompletionofadigitaltoanalogconversioncycle.TheconfigurationoftheD/AconverterissetupviathecontrolregisterDACC.

WavetableFunctionRegisters-CHANNEL_NUMBER,FREQ_NUMBER_H,FREQ_NUMBER_L,REPEAT_NUMBER_H,REPEAT_NUMBER_L,VOLUME_CONTROL,L_VOL,R_VOL

HT37A70/60/50/40/30/20containsWavetablesynthe-sizerFunction.TheHT37A70/60/50/40/30/20hasabuilt-in8outputchannels.CHANNEL_NUMBERischannelnumberselection.FREQ_NUMBER_HandFREQ_NUMBER_LareusedtodefinetheoutputspeedofthePCMfile.

START_ADDRESS_HandSTART_ADDRESS_LissetupforthestartaddressofthePCMcodebeforeWavetablefunctionimplement.Therepeatnumberreg-isterasknownREPEAT_NUMBER_HandRE-PEAT_NUMBER_Lareusedtodefinetheaddresswhichistherepeatpointofthesample.Whentherepeatnumberisdefined,itwillbeoutputfromthestartcodetotheendcodeonceandalwaysoutputtherangebe-tweentherepeataddresstotheendcode(80H)untilthevolumebecomeclose.Itprovidestheleftandrightvol-umecontrolindependently.The10-bitleftandrightvol-umearecontrolledbyVOLUME_CONTROL,L_VOL,andR_VOLrespectively.TheVOLUME_CONTROLcontainbothleftandrightvolumesomebitofhighbyte.ADPCMFunctionRegisters-ADR,XSPL,XSPH,ADPC,ADPS

HT37A70/60/50/40/30/20containsADPCMDecoderFunction.ThemustsetinitialvalueofregisterknownasXSPLandXSPHbeforeimplementingADPCMDecoderprocedure.Therearetwo4-bitADPCMencodedataofADR.ThedataofADRimplementviaADPCMDecoder,andoutput8-bitPCMdatawhichissynthesizedbyMIDIsynthesizer.

TheADPCisthecontrolregisterfortheADPCMDe-coder.TheADPSisthestatusregisterfortheADPCMDecoder.

CR/FConverterRegisters-ASCR,TMRAH,TMRAL,RCOCCR,TMRBH,TMRBL,RCOCR

Thereare8analogswitchlinesinthemicrocontrollerforK0~K7forHT37A70/60/50/40/30,exceptHT37A20whichonlyhave4analogswitchlinesforK0~K3andacorrespondingAnalogSwitchcontrolregistersknownasASCR.TheRCoscillationconvertercontainstwo16-bitprogrammablecount-upcountersandtheTimerAclocksourcemaycomefromthesystemclock(fSYS=fOSC/2)orsystemclock/4(fOSC/8).Therearetwodataregisters,ahighbytedataregisterknownasTMRAH,andalowbytedataregisterknownasTMRAL.ThetimerBclocksourcemaycomefromtheexternalRCoscillator.Therearetwodataregisters,ahighbytedataregisterknownasTMRBH,andalowbytedataregisterknownasTMRBL.TherearetwocontrolandstatusregistersknownasRCOCCRandRCOCR.

Rev.1.0026February17,2009

HT37A70/60/50/40/30/20A/DConverterRegisters-ADRL,ADRH,ADCR,ACSR

HT37A70/60/50/40containsa8-channel12-bitA/Dconverter.ThecorrectoperationoftheA/Drequirestheuseoftwodataregisters,acontrolregisterandaclocksourceregister.Itcontaina12-bitA/Dconverter,therearetwodataregisters,ahighbytedataregisterknownasADRH,andalowbytedataregisterknownasADRL.Thesearetheregisterlocationswherethedigitalvalueisplacedafterthecompletionofananalogtodigitalcon-versioncycle.ThechannelselectionandconfigurationoftheA/DconverterissetupviathecontrolregisterADCRwhiletheA/Dclockfrequencyisdefinedbytheclocksourceregister,ACSR.HT37A30/20wasnotinte-gratedA/Dconverter.

Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePA0~PA7pinsfromhightolow.AfteraHALTinstruc-tionforcesthemicrocontrollerintoenteringthePowerDownMode,theprocessorwillremainidleorinalow-powerstateuntilthelogicconditionoftheselectedwake-uppinonPortAchangesfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.NotethatpinsPA0toPA7canbeselectedindividuallytohavethiswake-upfeatureusinganPAwakeupoption,locatedinthecon-figuration.

I/OPortControlRegisters

EachI/Oporthavetheirowncontrolregister,knownasPAC,PAB,PCCandPDC,whichcontroltheinput/out-putconfiguration.Withthiscontrolregister,eachPA~PDI/Opinwithorwithoutpull-highresistorscanberecon-figuredbypull-hioptioncontrol.PinsPA~PDportsaredirectlymappedtoabitinitsassociatedportcontrolreg-ister.FortheI/Opintofunctionasaninput,thecorre-spondingbitofthecontrolregistermustbewrittenasa²1².Thiswillthenallowthelogicstateoftheinputpintobedirectlyreadbyinstructions.Whenthecorrespond-ingbitofthecontrolregisteriswrittenasa²0²,theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.

However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.

·Pin-sharedFunctions

Input/OutputPorts

HoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Withtheinputoroutputdesignationofev-erypinfullyunderuserprogramcontrol,pull-highop-tionsforallportsandwake-upoptionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.De-pendinguponwhichdeviceorpackageischosen,themicrocontrollerrangeprovidesfrom16to28bidirectionalinput/outputlineslabeledwithportnamesPA,PB,PCandPD.TheseI/OportsaremappedtotheRAMDataMemorywithspecificaddressesasshownintheSpecialPurposeDataMemorytable.AlloftheseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction²MOVA,[m]²,wheremdenotestheportad-dress.

Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.Pull-highResistors

Manyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexter-nalresistor.Toeliminatetheneedfortheseexternalre-sistors,I/OpinsPA~PD,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectableviaPA~PDoptionrespectively,locatedintheconfiguration.Thepull-highresistorsareimplementedusingweakPMOStransistors.PortAWake-up

IftheHALTinstructionisexecuted,thedevicewillenterthePowerDownMode,wherethesystemclockwillstopresultinginpowerbeingconserved,afeaturethatisim-portantforbatteryandotherlow-powerapplications.

Theflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyofthesedifficultiescanbeovercome.Forsomepins,thechosenfunctionofthemulti-functionI/Opinsissetbyconfigurationoptionswhileforothersthefunctionissetbyapplicationpro-gramcontrol.

·ExternalInterruptInput

Theexternalinterruptpin,INT,ispin-sharedwiththeI/OpinPA5.Tousethepinasanexternalinterruptin-putthecorrectbitsinthePAsharepinoptionmustbeselected.ThepinmustalsobesetupasaninputbysettingtheappropriatebitinthePortControlRegister.Apull-highresistorcanalsobeselectedviatheappro-priateportpull-highoption.

Rev.1.0027February17,2009

HT37A70/60/50/40/30/20·A/DInputs

TheHT37A70/60/50/40have8A/Dconverterchannelinputs.Alloftheseanaloginputsarepin-sharedwithPB0toPB7.IfthesepinsaretobeusedasA/DinputsandnotasnormalI/OpinsthenthecorrespondingbitsintheA/DConverterControlRegister,ADCR.3~5andADSR.4,mustbeproperlyset.Therearenoconfigu-rationoptionsassociatedwiththeA/Dfunction.IfusedasI/Opins,thenfullpull-highresistorselectionsremain,howeverifusedasA/Dinputsthenanypull-highresistorselectionsassociatedwiththesepinswillbeautomaticallydisconnected.

·CR/FanalogswitchInputs

theexactlogicalconstructionoftheI/Opinmaydifferfromthesedrawings,theyaresuppliedasaguideonlytoassistwiththefunctionalunderstandingoftheI/Opins.

ProgrammingConsiderations

Withintheuserprogram,oneofthefirstthingstocon-siderisportinitialization.Afterareset,thePA~PDdataregisterandPAC~PDCportcontrolregisterwillbesethigh.ThismeansthatallI/Opinswilldefaulttoaninputstate,thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highoptionshavebeense-lected.IfthePACportcontrolregister,isthenpro-grammedtosetupsomepinsasoutputs,theseoutputpinswillhaveaninitialhighoutputvalueunlesstheas-sociatedPAportdataregisterisfirstprogrammed.Se-lectingwhichpinsareinputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvalueintotheportcontrolregisterorbyprogrammingindividualbitsintheportcontrolregisterusingthe²SET[m].i²and²CLR[m].i²instructions.

Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenre-writethisdatabacktotheoutputports.

TheHT37A70/60/50/40/30have8CR/Fconverterin-puts.Alloftheseanaloginputsarepin-sharedwithPC0toPC7.IfthesepinsaretobeusedasCR/Fana-logswitchInputsandnotasnormalI/OpinsthenthecorrespondingbitsintheOption,²PC0~7sharepinconfiguration².TheHT37A20have4CR/Fconverterinputs.Alloftheseanaloginputsarepin-sharedwithPC0toPC3.IfthesepinsaretobeusedasCR/Fana-logswitchInputsandnotasnormalI/Opinsthenthecorrespondingbitsintheconfiguration,²PC0~3sharepinconfiguration².

·CR/Foscillatorpin

TheHT37A70/60/50/40/30/20have4CR/Foscillatorpins.AlloftheseCR/Foscillatorpinarepin-sharedwithPD0toPD3.IfthesepinsaretobeusedasCR/Foscil-latorpinsandnotasnormalI/Opinsthenthecorre-spondingbitsintheOption,²PD0~3sharepinOption².I/OPinStructures

ThediagramsillustratetheI/Opininternalstructures.As

Read/WriteTiming

Input/OutputPort

Rev.1.0028February17,2009

HT37A70/60/50/40/30/20Timer/EventCounters

Theprovisionoftimersformanimportantpartofanymicrocontroller,givingthedesignerameansofcarryingouttimerelatedfunctions.Thedevicescontaintwocount-uptimers8-bitcapacityandonecount-uptimers16-bitcapacity.Asthetimer0/1hasthreedifferentoper-atingmodes,theycanbeconfiguredtooperateasageneraltimer,anexternaleventcounterorasapulsewidthmeasurementdevice.Butthetimer2onlybecon-figuredtooperateasageneraltimer.Theprovisionofaninternalprescalertotheclockcircuitryofsomeofthetimer/eventcountersgivesaddedrangetothetimer1/2.TherearethreetypesofregistersrelatedtotheTimer/EventCounters0.Thefirsttworegistercontaintheactualhighandlowbytevalueofthetimerandintowhichaninitialvaluecanbepreloaded.TherearetwotypesofregistersrelatedtotheTimer/EventCounters1/2.Thefirstistheregisterthatcontainstheactualvalueofthetimerandintowhichaninitialvaluecanbepreloaded.ReadingfromthisregisterretrievesthecontentsoftheTimer/EventCounter.ThesecondtypeofassociatedregisteristheTimerControlRegisterwhichdefinesthetimeroptionsanddeter-mineshowthetimeristobeused.TheTimer/EventCounter0canhavethetimerclockconfiguredtocomefromtheinternalclocksource.TheclocksourceisfOSC/8.Inaddition,thetimerclocksourceofTimer/EventCounter0canalsobeconfiguredtocomefromaninter-nalRC12kHz.

16-bitTimer/EventCounter0Structure8-bitTimer/EventCounter1Structure8-bitTimerCounter2Structure

Rev.1.00

February17,2009

HT37A70/60/50/40/30/20ConfiguringtheTimer/EventCounterInputClockSource

Theinternaltimer¢sclockcanoriginatefromvarioussources,dependingupontimerischosen.Thesystemclockinputtimersourceisusedwhenthetimerisinthetimermodeorinthepulsewidthmeasurementmode.ForTimer/EventCounter0,thesesystemclocktimersourceisselectedbyTMR0C.5.

ForTimer/EventCounter1,2thissystemclocktimersourceisfirstdividedbyaprescaler,thedivisionratioofwhichisconditionedbytheTimerControlRegisterbitsT1PSC0~T1PSC2.

Anexternalclocksourceisusedwhenthetimerisintheeventcountingmode,theclocksourcebeingprovidedontheexternaltimerpin,knownasTMR0orTMR1.Theseexternaltimerpinsarepin-sharedwithotherI/Opins.DependingupontheconditionofPAsharepinop-tion,eachhightolow,orlowtohightransitionontheex-ternaltimerinputpinwillincrementthecounterbyone.TimerRegisters-TMR0H/TMR0L,TMR1,TMR2ThetimerregistersarespecialfunctionregisterslocatedinthespecialpurposeDataMemoryandistheplacewheretheactualtimervalueisstored.Forthe8-bittimer,thisregisterisknownasTimer/EventCounter1/2.Inthecaseofthe16-bittimer,apairof8-bitregistersarere-quiredtostorethe16-bittimervalues.TheseareknownasTMR1L/TMR1H.Thevalueinthetimerregistersin-creasesbyoneeachtimeaninternalclockpulseisre-ceivedoranexternaltransitionoccursontheexternaltimerpin.ThetimerwillcountfromtheinitialvalueloadedbythepreloadregistertothefullcountofFFHforthe8-bittimerorFFFFHforthe16-bittimers,atwhichpointthetimeroverflowsandatimerinternalinterruptsignalis

generated.Thetimervaluewillthenberesetwiththeini-tialpreloadregistervalueandcontinuecounting.NotethattoachieveamaximumfullrangecountofFFHforthe8-bittimerorFFFFHforthe16-bittimers,thepreloadregistersmustfirstbeclearedtoallzeros.Itshouldbenotedthatafterpower-on,thepreloadregis-terswillbeinanunknowncondition.NotethatiftheTimer/EventCountersareinanOFFconditionanddataiswrittentotheirpreloadregisters,thisdatawillbeim-mediatelywrittenintotheactualcounter.However,ifthecounterisenabledandcounting,anynewdatawrittenintothepreloaddataregisterduringthisperiodwillre-maininthepreloadregisterandwillonlybewrittenintotheactualcounterthenexttimeanoverflowoccurs.Notealsothatwhenthetimerregistersareread,thetimerclockwillbeblockedtoavoiderrors,however,asthismayresultincertaintimingerrors,programmersmusttakethisintoaccount.

The16-bitTimer/EventCounterhavecontainedbothlowbyteandhighbytetimerregisters,accessingtheseregistersiscarriedoutinaspecificway.Itmustbenotedthatwhenusinginstructionstopreloaddataintothelowbyteregister,namelyTMR0L,thedatawillonlybeplacedinalowbytebufferandnotdirectlyintothelowbyteregister.Theactualtransferofthedataintothelowbyteregisterisonlycarriedoutwhenawritetoitsasso-ciatedhighbyteregister,namelyTMR0H,isexecuted.Ontheotherhand,usinginstructionstopreloaddataintothehighbytetimerregisterwillresultinthedatabe-ingdirectlywrittentothehighbyteregister.Atthesametimethedatainthelowbytebufferwillbetransferredintoitsassociatedlowbyteregister.Forthisreason,whenpreloadingdataintothe16-bittimerregisters,thelowbyteshouldbewrittenfirst.Itmustalsobenotedthattoreadthecontentsofthelowbyteregister,areadtothe

Timer/EventCounter0ControlRegister

Rev.1.00

February17,2009

HT37A70/60/50/40/30/20Timer/EventCounter1ControlRegister

TimerCounter2ControlRegister

Rev.1.0031February17,2009

HT37A70/60/50/40/30/20highbyteregistermustfirstbeexecutedtolatchthecon-tentsofthelowbytebufferintoitsassociatedlowbyteregister.Afterthishasbeendone,thelowbyteregistercanbereadinthenormalway.Notethatreadingthelowbytetimerregisterwillonlyresultinreadingtheprevi-ouslylatchedcontentsofthelowbytebufferandnottheactualcontentsofthelowbytetimerregister.

TimerControlRegisters-TMR0C,TMR1C,TMR2CTheTimer/EventCounters0/1enablethemtooperateinthreedifferentmodes.theoptionsofwhicharedeter-minedbythecontentsoftheirrespectivecontrolregis-ter.Therearefourtimercontrolregisters,knownasTMR0C,TMR1CandTMR2C.Itisthetimercontrolreg-istertogetherwithitscorrespondingtimerregistersthatcontrolthefulloperationoftheTimer/EventCounters.Beforethetimerscanbeused,itisessentialthattheap-propriatetimercontrolregisterisfullyprogrammedwiththerightdatatoensureitscorrectoperation,aprocessthatisnormallycarriedoutduringprograminitialization.Tochoosewhichofthethreemodesthetimeristooper-atein,eitherinthetimermode,theeventcountingmodeorthepulsewidthmeasurementmode,bits7and6oftheTimerControlRegister,whichareknownasthebitpairT0M1/T0M0,T1M1/T1M0respectively,dependinguponwhichtimerisused,mustbesettotherequiredlogiclevels.Thetimer-onbit,whichisbit4oftheTimerControlRegisterandknownasT0ON,T1ONorT2ON,dependinguponwhichtimerisused,providesthebasicon/offcontroloftherespectivetimer.Settingthebithighallowsthecountertorun,clearingthebitstopsthecoun-ter.Ifthetimerisintheeventcountorpulsewidthmea-surementmode,theactivetransitionedgeleveltypeisselectedbythelogiclevelofbit3oftheTimerControlRegisterwhichisknownasT0E,T1EorT2E,depend-inguponwhichtimerisused.ConfiguringtheTimerMode

Inthismode,thetimercanbeutilizedtomeasurefixedtimeintervals,providinganinternalinterruptsignaleachtimethecounteroverflows.Tooperateinthismode,bitsTM1andTM0oftheTMR0C~TMR2Cregistermustbesetto1and0respectively.Inthismode,theinternalclockisusedasthetimerclock.Theinputclockfre-quencyof16bittimertothetimerisfOSC/8andRC12K,selectedbyTMR0C.5.Theinputclockfrequencyof8bittimertothetimerisFoscdividedbythevaluepro-grammedintothetimerprescaler,thevalueofwhichis

determinedbybitsPSC0~PSC2oftheTMR1C~TMR2Cregister.Thetimer-onbit,TONmustbesethightoenablethetimertorun.Eachtimeaninternalclockhightolowtransitionoccurs,thetimerincrementsbyone.Whenthetimerisfullandoverflows,thetimerwillberesettothevaluealreadyloadedintothepreloadreg-isterandcontinuecounting.Ifthetimerinterruptisen-abled,aninterruptsignalwillalsobegenerated.ThetimerinterruptcanbedisabledbyensuringthattheET0I~ET2IbitintheINTCandINTCHregistersisclearedtozero.Itshouldbenotedthatatimeroverflowisoneofthewake-upsources.ConfiguringtheEventCounterMode

Inthismode,twonumberofexternallychanginglogicevents,occurringonexternalpinPA6/TMR0orPA7/TMR1,canberecordedbytheinternaltimer.Forthetimertooperateintheeventcountingmode,bitsTM1andTM0oftheTMR0CorTMR1Cregistersmustbesetto0and1respectively.Thetimer-onbit,TONmustbesethightoenablethetimertocount.WithTElow,thecounterwillincrementeachtimethePA6/TMR0orPA7/TMR1pinreceivesalowtohightransition.IftheTEbitishigh,thecounterwillincrementeachtimePA6/TMR0orPA7/TMR1pinreceivesahightolowtran-sition.Asinthecaseoftheothertwomodes,whenthecounterisfullandoverflows,thetimerwillberesettothevaluealreadyloadedintothepreloadregisterandcon-tinuecounting.Ifthetimerinterruptisenabled,aninter-ruptsignalwillalsobegenerated.

ThetimerinterruptcanbedisabledbyensuringthattheETIbitintheINTCandINTCHregistersisclearedtozero.ToensurethattheexternalpinPA6/TMR0orPA7/TMR1isconfiguredtooperateasaneventcounterinputpin,twothingshavetohappen.Thefirstistoen-surethattheTM0andTM1bitsplacethetimer/eventcounterintheeventcountingmode,thesecondistoen-surethatthesharepinMR0orTMR1areselectedbyoption.Itshouldbenotedthatatimeroverflowisoneofthewake-upsources.AlsointheEventCountingmode,theTimer/EventCounterwillcontinuetorecordexter-nallychanginglogiceventsonthetimerinputpin,evenifthemicrocontrollerisinthePowerDownMode.Asare-sultwhenthetimeroverflowsitwillgenerateawake-upandiftheinterruptsareenabledalsogenerateatimerinterruptsignal.

TimerModeTimingDiagram

Rev.1.0032February17,2009

HT37A70/60/50/40/30/20EventCounterModeTimingDiagram

ConfiguringthePulseWidthMeasurementModeInthismode,thewidthofexternalpulsesappliedtothepin-sharedexternalpinPA6/TMR0orPA7/TMR1canbemeasured.InthePulseWidthMeasurementMode,thetimerclocksourceissuppliedbytheinternalclock.Forthetimertooperateinthismode,bitsTM0andTM1mustbothbesethigh.IftheTEbitislow,onceahightolowtransitionhasbeenreceivedonthePA6/TMR0orPA7/TMR1pin,thetimerwillstartcountinguntilthePA6/TMR0orPA7/TMR1pinreturnstoitsoriginalhighlevel.AtthispointtheTONbitwillbeautomaticallyresettozeroandthetimerwillstopcounting.IftheTEbitishigh,thetimerwillbegincountingoncealowtohightransitionhasbeenreceivedonthePA6/TMR0orPA7/TMR1pinandstopcountingwhenthePA6/TMR0orPA7/TMR1pinreturnstoitsoriginallowlevel.Asbe-fore,theTONbitwillbeautomaticallyresettozeroandthetimerwillstopcounting.ItisimportanttonotethatinthePulseWidthMeasurementMode,theTONbitisau-tomaticallyresettozerowhentheexternalcontrolsignalontheexternaltimerpinreturnstoitsoriginallevel,whereasintheothertwomodestheTONbitcanonlyberesettozerounderprogramcontrol.Theresidualvalueinthetimer,whichcannowbereadbytheprogram,thereforerepresentsthelengthofthepulsereceivedonpinPA6/TMR0orPA7/TMR1.AstheTONbithasnowbeenresetanyfurthertransitionsonthePA6/TMR0orPA7/TMR1pinwillbeignored.NotuntiltheTONbitisagainsethighbytheprogramcanthetimerbeginfur-therpulsewidthmeasurements.Inthiswaysingleshotpulsemeasurementscanbeeasilymade.Itshouldbenotedthatinthismodethecounteriscontrolledbylogi-caltransitionsonthePA6/TMR0orPA7/TMR1pinandnotbythelogiclevel.

Prescaler

BitsPSC0~PSC2oftheTMRC1~TMRC2registerscanbeusedtodefinethepre-scalingstagesoftheinternalclocksourcesoftheTimer/EventCounter.

Note:BecausethetwotimersareusedbyMIDItheex-ternaltimerpinfunctionsaredisabled.I/OInterfacing

TheTimer/EventCounter,whenconfiguredtorunintheeventcounterorpulsewidthmeasurementmode,re-quiretheuseoftheexternalPA6/TMR0orPA7/TMR1pinforcorrectoperation.AsthispinisasharedpinitmustbeconfiguredcorrectlytoensureitissetupforuseasaTimer/EventCounterinputandnotasanormalI/Opin.Thisisimplementedbyensuringthatthemodese-lectbitsintheTimer/EventCountercontrolregister,se-lecteithertheeventcounterorpulsewidthmeasurementmode.AdditionallythePAsharepinop-tionmustbeselectedtoensurethatthepinissetupasanTMR0andTMR1input.ProgrammingConsiderations

Whenconfiguredtoruninthetimermode,theinternalsystemclockfOSC/8isusedasthetimerclocksourceandisthereforesynchronizedwiththeoveralloperationofthemicrocontroller.Inthismodewhentheappropriatetimerregisterisfull,themicrocontrollerwillgenerateaninternalinterruptsignaldirectingtheprogramflowtotherespectiveinternalinterruptvector.Forthepulsewidthmeasurementmode,theinternalsystemclockisalsousedasthetimerclocksourcebutthetimerwillonlyrunwhenthecorrectlogicconditionappearsontheexternaltimerinputpin.Asthisisanexternaleventandnotsyn-chronizedwiththeinternaltimerclock,themicrocontrollerwillonlyseethisexternaleventwhenthenexttimerclockpulsearrives.Asaresult,theremaybe

PulseWidthMeasureModeTimingDiagram

Rev.1.0033February17,2009

HT37A70/60/50/40/30/20smalldifferencesinmeasuredvaluesrequiringpro-grammerstotakethisintoaccountduringprogramming.Thesameappliesifthetimerisconfiguredtobeintheeventcountingmode,whichagainisanexternaleventandnotsynchronizedwiththeinternalsystemortimerclock.WhentheTimer/EventCounterisread,orifdataiswrittentothepreloadregister,theclockisinhibitedtoavoiderrors,howeverasthismayresultinacountinger-ror,thisshouldbetakenintoaccountbytheprogram-mer.Caremustbetakentoensurethatthetimersareproperlyinitializedbeforeusingthemforthefirsttime.Theassociatedtimerenablebitsintheinterruptcontrolregistermustbeproperlysetotherwisetheinternalin-terruptassociatedwiththetimerwillremaininactive.Theedgeselect,timermodeandclocksourcecontrolbitsintimercontrolregistermustalsobecorrectlysettoensurethetimerisproperlyconfiguredfortherequiredapplication.Itisalsoimportanttoensurethataninitialvalueisfirstloadedintothetimerregistersbeforethetimerisswitchedon;thisisbecauseafterpower-ontheinitialvaluesofthetimerregistersareunknown.AfterthetimerhasbeeninitializedthetimercanbeturnedonandoffbycontrollingtheenablebitinthetimercontrolTimerProgramExample

ThisprogramexampleshowshowtheTimer/EventCounterregistersaresetup,alongwithhowtheinterruptsareen-abledandmanaged.NotehowtheTimer/EventCounteristurnedon,bysettingbit4oftheTimerControlRegister.TheTimer/EventCountercanbeturnedoffinasimilarwaybyclearingthesamebit.

ThisexampleprogramsetstheTimer/EventCountertobeinthetimermode,whichusestheinternalsystemclockastheclocksource.ShowhowtocounterTMR0=1kHz,TMR1=2kHz,TMR2=4kHz,iffOSCis11.059MHz.org00h;Resetjmpbeginorg04h;externalinterruptvectorretiorg08h;Timer/EventCounter0interruptvectorjmptmr0int;jumpherewhenTimer0overflowsorg0ch;Timer/EventCounter1interruptvectorjmptmr1int;jumpherewhenTimer1overflowsorg10h;TimerCounter2interruptvectorjmptmr2int;jumpherewhenTimer2overflowsorg20h;mainprogram

;internalTimer0,1,2Counterinterruptroutinetmr0int:

;Timer/EventCounter0mainprogramplacedhere:reti

tmr1int:

;Timer/EventCounter1mainprogramplacedhere:reti

tmr2int:

;TimerCounter2mainprogramplacedhere:reti:

begin:

;setupinterruptregistermova,0bh;enablemasterinterrupt,timer0andtimer1interruptmovintc,aRev.1.00

February17,2009

register.Notethatsettingthetimerenablebithightoturnthetimeron,shouldonlybeexecutedafterthetimermodebitshavebeenproperlysetup.Settingthetimerenablebithightogetherwithamodebitmodification,mayleadtoimpropertimeroperationifexecutedasasingletimercontrolregisterbytewriteinstruction.WhentheTimer/Eventcounteroverflows,itscorrespondingin-terruptrequestflagintheinterruptcontrolregisterwillbeset.Ifthetimerinterruptisenabledthiswillinturngener-ateaninterruptsignal.Howeverirrespectiveofwhethertheinterruptsareenabledornot,aTimer/Eventcounteroverflowwillalsogenerateawake-upsignalifthede-viceisinaPower-downcondition.ThissituationmayoccuriftheTimer/EventCounterisintheEventCountingModeandiftheexternalsignalcontinuestochangestate.Insuchacase,the

Timer/EventCounterwillcontinuetocounttheseexter-naleventsandifanoverflowoccursthedevicewillbewokenupfromitsPower-downcondition.Topreventsuchawake-upfromoccurring,thetimerinterruptre-questflagshouldfirstbesethighbeforeissuingtheHALTinstructiontoenterthePowerDownMode.

HT37A70/60/50/40/30/20mova,01hmovintch,a

;setupTimer0registersmova,low(65536-1382)movTMR0L,a;

mova,high(65536-1382)movTMR0H,a;mova,080hmovtmr0c,asettmr0c.4movmovmovmovsetmovmovmovmovset

a,low(256-173)TMR1,a;a,080htmr1c,atmr1c.4

a,low(256-173)TMR2,a;a,080htmr2c,atmr2c.4

;enabletimer2interrupt

;setupTimerpreloadlowbytevalue,interruptin1kHz;setupTimerpreloadhighbytevalue

;setupTimer0controlregister

;timermodeandclocksourceisfOSC/8®0.7234ms

;startTimer-notemodebitsmustbepreviouslysetup;setupTimerpreloadvalue,interruptin2kHz

;setupTimer1controlregister

;timermodeandPrescaleroutputisfOSC/32®2.ms;startTimer-notemodebitsmustbepreviouslysetup;setupTimerpreloadvalue,interruptin4kHz

;setupTimer2controlregister

;timermodeandPrescaleroutputisfOSC/16®1.447ms;startTimer-notemodebitsmustbepreviouslysetup

Interrupts

Interruptsareanimportantpartofanymicrocontrollersystem.WhenanexternaleventoraninternalfunctionsuchasaTimer/EventCounter0/1/2orERCOCIre-quireoranADPCMemptyrequiresmicrocontrollerat-tention,theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthemicrocontrollertodirectattentiontotheirrespectiveneeds.Eachdeviceinthisseriescontainsasingleex-ternalinterruptandtwointernalinterruptsfunctions.Theexternalinterruptiscontrolledbytheactionoftheexter-nalINTpin,whiletheinternalinterruptsarecontrolledbytheTimer/Event0/1CounteroverfloworERCOCIre-quireortheADPCMemptyinterrupt.InterruptRegister

Overallinterruptcontrol,whichmeansinterruptenablingandrequestflagsetting,iscontrolledbyINTCandINTCHregisters,whicharelocatedinDataMemory.Bycontrollingtheappropriateenablebitsinthisregistereachindividualinterruptcanbeenabledordisabled.Alsowhenaninterruptoccurs,thecorrespondingre-questflagwillbesetbythemicrocontroller.Theglobalenableflagifclearedtozerowilldisableallinterrupts.

InterruptOperation

Timer/Event0/1/2Counteroverflow,ERCOCIinterrupt,ADPCMemptyrequestortheexternalinterruptlinebe-ingpulledlowwillallgenerateaninterruptrequestbysettingtheircorrespondingrequestflag,iftheirappropri-ateinterruptenablebitisset.Whenthishappens,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorrespond-inginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.TheinstructionatthisvectorwillusuallybeaJMPstatementwhichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.TheinterruptserviceroutinemustbeterminatedwithaRETIstatement,whichretrievestheoriginalProgramCounteraddressfromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.

Rev.1.0035February17,2009

HT37A70/60/50/40/30/20Onceaninterruptsubroutineisserviced,alltheotherin-terruptswillbeblocked,astheEMIbitwillbeclearedau-tomatically.

Thiswillpreventanyfurtherinterruptnestingfromoc-curring.However,ifotherinterruptrequestsoccurdur-ingthisinterval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillbere-corded.Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtherou-tine,toallowinterruptnesting.Ifthestackisfull,thein-terruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.InterruptPriority

Interrupts,occurringintheintervalbetweentherisingedgesoftwoconsecutiveT2pulses,willbeservicedonthelatterofthetwoT2pulses,ifthecorrespondinginter-ruptsareenabled.Incaseofsimultaneousrequests,thefollowingtableshowstheprioritythatisapplied.ThesecanbemaskedbyresettingtheEMIbit.Incaseswherebothexternalandinternalinterruptsareenabledandwhereanexternalandinternalinterruptoccurssimulta-neously,theexternalinterruptwillalwayshavepriorityandwillthereforebeservicedfirst.SuitablemaskingoftheindividualinterruptsusingtheINTCregistercanpre-ventsimultaneousoccurrences.

InterruptSource

Reset

ExternalInterrupt

Timer/EventCounter0OverflowTimer/EventCounter1OverflowTimerCounter2overflowERCOCIInterruptADPCMEmptyInterruptExternalInterrupt

Foranexternalinterrupttooccur,theglobalinterrupten-ablebit,EMI,andexternalinterruptenablebit,EEI,mustfirstbeset.Anactualexternalinterruptwilltakeplacewhentheexternalinterruptrequestflag,EIF,isset,asituationthatwilloccurwhenahightolowtransi-tionappearsontheINTline.Theexternalinterruptpinispin-sharedwiththeI/OpinPA5andcanonlybeconfig-uredasanexternalinterruptpinifthecorrespondingex-ternalinterruptenablebitintheINTCregisterhasbeenset.Thepinmustalsobeselectedasbysettingthecor-respondingPAC.5bitintheportcontrolregister.Whentheinterruptisenabled,thestackisnotfullandahightolowtransitionappearsontheexternalinterruptpin,asubroutinecalltotheexternalinterruptvectoratlocation04H,willtakeplace.Whentheinterruptisserviced,theexternalinterruptrequestflag,EIF,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodis-ableotherinterrupts.

Priority1234567

Vector00H04H08H0CH10H14H18H

InterruptLowByteControlRegister

Rev.1.0036February17,2009

HT37A70/60/50/40/30/20InterruptHighByteControlRegister

InterruptStructure

Rev.1.0037February17,2009

HT37A70/60/50/40/30/20Timer/EventCounterInterrupts

Foratimergeneratedinternalinterrupttooccur,thecor-respondinginternalinterruptenablebitmustbefirstset.EachdevicehavetwointernalTimerCounters,theTimer/EventCounter0interruptenableisbit2oftheINTCregisterandknownasET0I,theTimer/EventCounter1interruptenableisbit3oftheINTCregisterandknownasET1IandtheTimerCounter2interruptenableisbit0oftheINTCHregisterandisknownasET2I.AnactualTimer/EventCounterinterruptwillbeini-tializedwhentheTimer/EventCounterinterruptrequestflagisset,causedbyatimeroverflow.Eachdevicehastwotimers,theTimer/EventCounter0requestflagisbit5oftheINTCregisterandknownasT0F,theTimer/EventCounter1requestflagisbit6oftheINTCregisterandknownasT1F,andtheTimerCounter2re-questflagisbit4oftheINTCHregisterandisknownasT2F.

Whenthemasterinterruptglobalenablebitisset,thestackisnotfullandthecorrespondingtimerinterrupten-ablebitisset,aninternalinterruptwillbegeneratedwhenthecorrespondingtimeroverflows.EachdevicehavetwointernalTimer/EventCounters,asubroutinecalltolocation08HwilloccurforTimer/EventCounter0,asubroutinecalltolocation0CHforTimer/EventCoun-ter1,asubroutinecalltolocation10HforTimerCounter2.Afterenteringthetimerinterruptexecutionroutine,thecorrespondingtimerinterruptrequestflag,either,T0F,T1ForT2FwillberesetandtheEMIbitwillbeclearedtodisableotherinterrupts.RC/FInterrupt

TheexternalRCOscillationConverterinterruptisinitial-izedbysettingtheexternalRCOscillationConverterin-terruptrequestflag,RCOCF;bit5ofINTCH.ThisiscausedbyaTimerAorTimerBoverflow.Whenthein-terruptisenabled,andthestackisnotfullandtheRCOCFbitisset,asubroutinecalltolocation²14H²willoccur.

Therelatedinterruptrequestflag,RCOCF,willberesetandtheEMIbitclearedtodisablefurtherinterrupts.

ADPCMInterrupt

TheinternalADPCMinterruptisinitializedbysettingtheADPCMinterruptrequestflag(ADPCMF:bit6,CH0F:bit3andCH1F:bit7ofINTCH).TheCH0FandCH1FsetbyADR0orADR1emptyrespectively.TheADPCMFissetbyADR0orADR1emptyimmediately.Whentheinterruptisenabled,andthestackisnotfullandtheT0Fbitisset,asubroutinecalltolocation18Hwilloccur.TherelatedinterruptrequestADPCMFandCH0F/CH1FflagwillberesetandtheEMIbitclearedtodisablefurtherinterrupts.ProgrammingConsiderations

TheinterruptrequestflagsT0F,T1F,T2F,ADPCMF,CH0F,CH1F,togetherwiththeinterruptenablebitsET0I,ET1I,ET2I,EADPCM,formtheinterruptcontrolregistersINTC,INTCHwhicharelocatedintheDataMemory.Bydisablingtheinterruptenablebits,are-questedinterruptcanbepreventedfrombeingserviced,however,onceaninterruptrequestflagisset,itwillre-maininthisconditionintheINTCorINTCHregisteruntilthecorrespondinginterruptisservicedoruntilthere-questflagisclearedbyasoftwareinstruction.Itisrec-ommendedthatprogramsdonotusethe²CALLsubroutine²instructionwithintheinterruptsubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediatelyinsomeapplications.Ifonlyonestackisleftandtheinterruptisnotwellcon-trolled,theoriginalcontrolsequencewillbedamagedoncea²CALLsubroutine²isexecutedintheinterruptsubroutine.

AlloftheseinterruptshavethecapabilityofwakinguptheprocessorwheninthePowerDownMode.OnlytheProgramCounterispushedontothestack.Ifthecon-tentsoftheregisterorstatusregisterarealteredbytheinterruptserviceprogram,whichmaycorruptthede-siredcontrolsequence,thenthecontentsshouldbesavedinadvance.

Rev.1.0038February17,2009

HT37A70/60/50/40/30/20ResetandInitialisation

Aresetfunctionisafundamentalpartofanymicrocontrollerensuringthatthedevicecanbesettosomepredeterminedconditionirrespectiveofoutsideparameters.Themostimportantresetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase,internalcircuitrywillensurethatthemicrocontroller,af-terashortdelay,willbeinawelldefinedstateandreadytoexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcom-mences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.

Inadditiontothepower-onreset,situationsmayarisewhereitisnecessarytoforcefullyapplyaresetconditionwhenthemicrocontrollerisrunning.Oneexampleofthisiswhereafterpowerhasbeenappliedandthemicrocontrollerisalreadyrunning,theRESlineisforce-fullypulledlow.Insuchacase,knownasanormaloper-ationreset,someofthemicrocontrollerregistersremainunchangedallowingthemicrocontrollertoproceedwithnormaloperationaftertheresetlineisallowedtoreturnhigh.AnothertypeofresetiswhentheWatchdogTimeroverflowsandresetsthemicrocontroller.Alltypesofre-setoperationsresultindifferentregisterconditionsbe-ingsetup.

AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullreset,similartotheRESresetisimple-mentedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.ResetFunctions

Therearefivewaysinwhichamicrocontrollerresetcanoccur,througheventsoccurringbothinternallyandex-ternally:

·Power-onReset

inhibited.AftertheRESlinereachesacertainvoltagevalue,theresetdelaytimetRSTDisinvokedtoprovideanextradelaytimeafterwhichthemicrocontrollerwillbeginnormaloperation.TheabbreviationSSTinthefiguresstandsforSystemStart-upTimer.

FormostapplicationsaresistorconnectedbetweenVDDandtheRESpinandacapacitorconnectedbe-tweenVSSandtheRESpinwillprovideasuitableex-Power-OnResetTimingChart

ternalresetcircuit.AnywiringconnectedtotheRESpinshouldbekeptasshortaspossibletominimiseanystraynoiseinterference.

ForapplicationsthatoperatewithinanenvironmentwheremorenoiseispresenttheEnhancedResetCir-cuitshownisrecommended.

Moreinformationregardingexternalresetcircuitsis

BasicResetCircuit

locatedinApplicationNoteHA0075EontheHoltekwebsite.

·RESPinReset

Themostfundamentalandunavoidableresetistheonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryad-dress,apower-onresetalsoensuresthatcertainotherregistersarepresettoknownconditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthatallpinswillbefirstsettoinputs.

AlthoughthemicrocontrollerhasaninternalRCresetfunction,iftheVDDpowersupplyrisetimeisnotfastenoughordoesnotstabilisequicklyatpower-on,theinternalresetfunctionmaybeincapableofprovidingproperresetoperation.Forthisreasonitisrecom-mendedthatanexternalRCnetworkisconnectedtotheRESpin,whoseadditionaltimedelaywillensurethattheRESpinremainslowforanextendedperiodtoallowthepowersupplytostabilise.Duringthistimedelay,normaloperationofthemicrocontrollerwillbeRev.1.00

EnhancedResetCircuit

ThistypeofresetoccurswhenthemicrocontrollerisalreadyrunningandtheRESpinisforcefullypulledlowbyexternalhardwaresuchasanexternalswitch.Inthiscaseasinthecaseofotherreset,theProgramCounterwillresettozeroandprogramexecutioniniti-atedfromthispoint.

February17,2009

HT37A70/60/50/40/30/20RESResetTimingChart

·LowVoltageReset-LVR

Thedifferenttypesofresetdescribedaffecttheresetflagsindifferentways.Theseflags,knownasPDFandTOarelocatedinthestatusregisterandarecontrolledbyvariousmicrocontrolleroperations,suchasthePowerDownfunctionorWatchdogTimer.Theresetflagsareshowninthetable:TOPDF0u011

0u1u1

RESETConditions

RESresetduringpower-on

RESorLVRresetduringnormaloperationRESWake-upHALT

WDTtime-outresetduringnormaloperationWDTtime-outresetduringPowerDown

Themicrocontrollercontainsalowvoltageresetcir-cuitinordertomonitorthesupplyvoltageofthede-vice,whichisselectedviaaconfigurationoptionandTheVLVRcanselectas3.3V,3.0Vor2.2V.Ifthesup-plyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebattery,theLVRwillautomaticallyresetthedevicein-ternally.TheLVRincludesthefollowingspecifica-tions:ForavalidLVRsignal,alowvoltage,i.e.,avoltageintherangebetween0.9V~VLVRmustexistforgreaterthanthevaluetLVRspecifiedintheA.C.char-acteristics.Ifthelowvoltagestatedoesnotexceed1ms,theLVRwillignoreitandwillnotperformaresetfunction.

Note:²u²standsforunchanged

Thefollowingtableindicatesthewayinwhichthevari-ouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.

Item

ProgramCounter

ConditionAfterRESETResettozero

AllinterruptswillbedisabledClearafterreset,WDTbeginscounting

TimerCounterwillbeturnedoffTheTimerCounterPrescalerwillbecleared

InterruptsWDTTimer/EventCounterPrescaler

LowVoltageResetTimingChart

·WatchdogTime-outResetduringNormalOperation

TheWatchdogtime-outResetduringnormalopera-tionisthesameasahardwareRESpinresetexceptthattheWatchdogtime-outflagTOwillbesetto²1².

Input/OutputPortsI/OportswillbesetupasinputsStackPointer

StackPointerwillpointtothetopofthestack

WDTTime-outResetduringNormalOperation

TimingChart

·WatchdogTime-outResetduringPowerDown

Thedifferentkindsofresetsallaffecttheinternalregis-tersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontrollerisinafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectseachofthemicrocontrollerinternalregisters.

TheWatchdogtime-outResetduringPowerDownisalittledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthatthePro-gramCounterandtheStackPointerwillbeclearedto²0²andtheTOflagwillbesetto²1².RefertotheA.C.CharacteristicsfortSSTdetails.ResetInitialConditions

WDTTime-outResetduringPowerDown

TimingChartRev.1.00

February17,2009

HT37A70/60/50/40/30/20HT37A70/60

RegisterTMR0HTMR0LTMR0CTMR1LTMR1CTMR2LTMR2CPCLMP0MP1MP2RBP1RBP2BP1ACCTBLP1TBLHTBMP1TBHP1STATUSINTCINTCHPAPACPBPBCPCPCCPDPDCDACDAHDALCHANFreqNHFreqNLAddrHAddrLRepHRepLENV

Reset(Power-on)xxxxxxxxxxxxxxxx00001-- -xxxxxxxx00-01000xxxxxxxx00-0100000000000xxxxxxxxxxxxxxxxxxxxxxxx

- ------0- ------0

RESorLVRResetxxxxxxxxxxxxxxxx00001-- -xxxxxxxx00-01000xxxxxxxx00-0100000000000uuuuuuuuuuuuuuuuuuuuuuuu

- ------0- ------0

WDTTime-out(NormalOperation)xxxxxxxxxxxxxxxx00001-- -xxxxxxxx00-01000xxxxxxxx00-0100000000000uuuuuuuuuuuuuuuuuuuuuuuu

- ------0- ------0

WDTTime-out

(HALT)uuuuuuuuuuuuuuuuuuuuu-- -uuuuuuuuuu-uuuuuuuuuuuuuuu-uuuuu00000000uuuuuuuuuuuuuuuuuuuuuuuu

- ------u- ------u

xxx00000xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx--00xxxx-000000010001000111111111111111111111111111111111111111111111111----1111----111100000000xxxxxxxxxxxxxxxx00---000xxxxxxxxxxxxxxxx--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx-xxxxxx

xxx00000uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu--uuuuuu-000000010001000111111111111111111111111111111111111111111111111----1111----111100000000uuuuuuuuuuuuuuuu00---000uuuuuuuuuuuuuuuu--uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuu

xxx00000uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu--1uuuuu-000000010001000111111111111111111111111111111111111111111111111----1111----111100000000uuuuuuuuuuuuuuuu00---000uuuuuuuuuuuuuuuu--uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuu

xxx00000uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu--11uuuu-uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu----uuuu----uuuuuuuuuuuuuuuuuuuuuuuuuuuuuu---uuuuuuuuuuuuuuuuuuu--uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuu

Rev.1.0041February17,2009

HT37A70/60/50/40/30/20RegisterLVCRVCWDTSADRXSPLXSPHADPCADPSACSRADRLADRHADCRASCRTMRAHTMRALRCOCCRTMRBHTMRBLRCOCRNote:

Reset(Power-on)xxxxxxxxxxxxxxxx00000111xxxxxxxx000000000000000000-0--00----11111-----00xxxx----xxxxxxxx01000000----0000xxxxxxxxxxxxxxxx00001---xxxxxxxxxxxxxxxx------00

RESorLVRResetuuuuuuuuuuuuuuuu00000111xxxxxxxx000000000000000000-0--00----11111-----00xxxx----xxxxxxxx01000000----0000xxxxxxxxxxxxxxxx00001---xxxxxxxxxxxxxxxx------00

WDTTime-out(NormalOperation)uuuuuuuuuuuuuuuu00000111xxxxxxxx000000000000000000-0--00----11111-----00xxxx----xxxxxxxx01000000----0000xxxxxxxxxxxxxxxx00001---xxxxxxxxxxxxxxxx------00

WDTTime-out

(HALT)uuuuuuuuuuuuuuuu00000uuuuuuuuuuuuuuuuuuuuuuuuuuuuu-u--uu----uuuu1-----uuuuuu----uuuuuuuuu1uuuuuu----uuuuuuuuuuuuuuuuuuuuuuuuu---uuuuuuuuuuuuuuuu------uu

²u²standsforunchanged²x²standsforunknown

²-²standsforunimplemented

Rev.1.0042February17,2009

HT37A70/60/50/40/30/20HT37A50/40

RegisterTMR0HTMR0LTMR0CTMR1LTMR1CTMR2LTMR2CPCLMP0MP1MP2RBP1RBP2BP1ACCTBLP1TBLHTBMP1STATUSINTCINTCHPAPACPBPBCPCPCCPDPDCDACDAHDALCHANFreqNHFreqNLAddrHAddrLRepHRepLENVLVC

Reset(Power-on)xxxxxxxxxxxxxxxx00001-- -xxxxxxxx00-01000xxxxxxxx00-0100000000000xxxxxxxxxxxxxxxxxxxxxxxx

- ------0- ------0

RESorLVRResetxxxxxxxxxxxxxxxx00001-- -xxxxxxxx00-01000xxxxxxxx00-0100000000000uuuuuuuuuuuuuuuuuuuuuuuu

- ------0- ------0

WDTTime-out(NormalOperation)xxxxxxxxxxxxxxxx00001-- -xxxxxxxx00-01000xxxxxxxx00-0100000000000uuuuuuuuuuuuuuuuuuuuuuuu

- ------0- ------0

WDTTime-out

(HALT)uuuuuuuuuuuuuuuuuuuuu-- -uuuuuuuuuu-uuuuuuuuuuuuuuu-uuuuu00000000uuuuuuuuuuuuuuuuuuuuuuuu

- ------u- ------u

xxxx0000xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx--00xxxx-000000010001000111111111111111111111111111111111111111111111111----1111----111100000000xxxxxxxxxxxxxxxx00---000xxxxxxxxxxxxxxxx---xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx-xxxxxxxxxxxxxx

xxxx0000uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu--uuuuuu-000000010001000111111111111111111111111111111111111111111111111----1111----111100000000uuuuuuuuuuuuuuuu00---000uuuuuuuuuuuuuuuu---uuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuuuuuuuuu

xxxx0000uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu--1uuuuu-000000010001000111111111111111111111111111111111111111111111111----1111----111100000000uuuuuuuuuuuuuuuu00---000uuuuuuuuuuuuuuuu---uuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuuuuuuuuu

xxxx0000uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu--11uuuu-uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu----uuuu----uuuuuuuuuuuuuuuuuuuuuuuuuuuuuu---uuuuuuuuuuuuuuuuuuu---uuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuuuuuuuuu

Rev.1.0043February17,2009

HT37A70/60/50/40/30/20RegisterRVCWDTSADRXSPLXSPHADPCADPSACSRADRLADRHADCRASCRTMRAHTMRALRCOCCRTMRBHTMRBLRCOCRNote:

Reset(Power-on)xxxxxxxx00000111xxxxxxxx000000000000000000-0--00----11111-----00xxxx----xxxxxxxx01000000----0000xxxxxxxxxxxxxxxx00001---xxxxxxxxxxxxxxxx------00

RESorLVRResetuuuuuuuu00000111xxxxxxxx000000000000000000-0--00----11111-----00xxxx----xxxxxxxx01000000----0000xxxxxxxxxxxxxxxx00001---xxxxxxxxxxxxxxxx------00

WDTTime-out(NormalOperation)uuuuuuuu00000111xxxxxxxx000000000000000000-0--00----11111-----00xxxx----xxxxxxxx01000000----0000xxxxxxxxxxxxxxxx00001---xxxxxxxxxxxxxxxx------00

WDTTime-out

(HALT)uuuuuuuu00000uuuuuuuuuuuuuuuuuuuuuuuuuuuuu-u--uu----uuuu1-----uuuuuu----uuuuuuuuu1uuuuuu----uuuuuuuuuuuuuuuuuuuuuuuuu---uuuuuuuuuuuuuuuu------uu

²u²standsforunchanged²x²standsforunknown

²-²standsforunimplemented

Rev.1.0044February17,2009

HT37A70/60/50/40/30/20HT37A30

RegisterTMR0HTMR0LTMR0CTMR1LTMR1CTMR2LTMR2CPCLMP0MP1MP2RBP1RBP2BP1ACCTBLP1TBLHTBMP1STATUSINTCINTCHPAPACPCPCCPDPDCDACDAHDALCHANFreqNHFreqNLAddrHAddrLRepHRepLENVLVCRVCWDTS

Reset(Power-on)xxxxxxxxxxxxxxxx00001-- -xxxxxxxx00-01000xxxxxxxx00-0100000000000xxxxxxxxxxxxxxxxxxxxxxxx

- ------0- ------0

RESorLVRResetxxxxxxxxxxxxxxxx00001-- -xxxxxxxx00-01000xxxxxxxx00-0100000000000uuuuuuuuuuuuuuuuuuuuuuuu

- ------0- ------0

WDTTime-out(NormalOperation)xxxxxxxxxxxxxxxx00001-- -xxxxxxxx00-01000xxxxxxxx00-0100000000000uuuuuuuuuuuuuuuuuuuuuuuu

- ------0- ------0

WDTTime-out

(HALT)uuuuuuuuuuuuuuuuuuuuu-- -uuuuuuuuuu-uuuuuuuuuuuuuuu-uuuuu00000000uuuuuuuuuuuuuuuuuuuuuuuu

- ------u- ------u

xxxxx000xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx--00xxxx-00000001000100011111111111111111111111111111111----1111----111100000000xxxxxxxxxxxxxxxx00---000xxxxxxxxxxxxxxxx----xxxxxxxxxxxxxxxxxxxxxxxxxxxxx-xxxxxxxxxxxxxxxxxxxxxx00000111

xxxxx000uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu--uuuuuu-00000001000100011111111111111111111111111111111----1111----111100000000uuuuuuuuuuuuuuuu00---000uuuuuuuuuuuuuuuu----uuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuuuuuuuuuuuuuuuuu00000111

xxxxx000uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu--1uuuuu-00000001000100011111111111111111111111111111111----1111----111100000000uuuuuuuuuuuuuuuu00---000uuuuuuuuuuuuuuuu----uuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuuuuuuuuuuuuuuuuu00000111

xxxxx000uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu--11uuuu-uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu----uuuu----uuuuuuuuuuuuuuuuuuuuuuuuuuuuuu---uuuuuuuuuuuuuuuuuuu----uuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuuuuuuuuuuuuuuuuu00000uuu

Rev.1.0045February17,2009

HT37A70/60/50/40/30/20RegisterADRXSPLXSPHADPCADPSASCRTMRAHTMRALRCOCCRTMRBHTMRBLRCOCRNote:

Reset(Power-on)xxxxxxxx000000000000000000-0--00----1111----0000xxxxxxxxxxxxxxxx00001---xxxxxxxxxxxxxxxx------00

RESorLVRResetxxxxxxxx000000000000000000-0--00----1111----0000xxxxxxxxxxxxxxxx00001---xxxxxxxxxxxxxxxx------00

WDTTime-out(NormalOperation)xxxxxxxx000000000000000000-0--00----1111----0000xxxxxxxxxxxxxxxx00001---xxxxxxxxxxxxxxxx------00

WDTTime-out

(HALT)uuuuuuuuuuuuuuuuuuuuuuuuuu-u--uu----uuuu----uuuuuuuuuuuuuuuuuuuuuuuuu---uuuuuuuuuuuuuuuu------uu

²u²standsforunchanged²x²standsforunknown

²-²standsforunimplemented

Rev.1.0046February17,2009

HT37A70/60/50/40/30/20HT37A20

RegisterTMR0HTMR0LTMR0CTMR1LTMR1CTMR2LTMR2CPCLMP0MP1MP2RBP1RBP2BP1ACCTBLP1TBLHTBMP1TBHP1STATUSINTCINTCHPAPACPCPCCPDPDCDACCDAHDALCHANFreqNHFreqNLAddrHAddrLRepHRepLENVLVCRVC

Reset(Power-on)xxxxxxxxxxxxxxxx00001-- -xxxxxxxx00-01000xxxxxxxx00-0100000000000xxxxxxxxxxxxxxxxxxxxxxxx

- ------0- ------0

RESorLVRResetxxxxxxxxxxxxxxxx00001-- -xxxxxxxx00-01000xxxxxxxx00-0100000000000uuuuuuuuuuuuuuuuuuuuuuuu

- ------0- ------0

WDTTime-out(NormalOperation)xxxxxxxxxxxxxxxx00001-- -xxxxxxxx00-01000xxxxxxxx00-0100000000000uuuuuuuuuuuuuuuuuuuuuuuu

- ------0- ------0

WDTTime-out

(HALT)uuuuuuuuuuuuuuuuuuuuu-- -uuuuuuuuuu-uuuuuuuuuuuuuuu-uuuuu00000000uuuuuuuuuuuuuuuuuuuuuuuu

- ------u- ------u

xxxxxx00xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx--00xxxx-0000000100010001111111111111111----1111----1111----1111----1111000--000xxxxxxxxxxxxxxxx00---000xxxxxxxxxxxxxxxx-----xxxxxxxxxxxxxxxxxxxxxxxxxxxx-xxxxxxxxxxxxxxxxxxxxxx

xxxxxx00uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu--uuuuuu-0000000100010001111111111111111----1111----1111----1111----1111000--000uuuuuuuuuuuuuuuu00---000uuuuuuuuuuuuuuuu-----uuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuuuuuuuuuuuuuuuuu

xxxxxx00uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu--1uuuuu-0000000100010001111111111111111----1111----1111----1111----1111000--000uuuuuuuuuuuuuuuu00---000uuuuuuuuuuuuuuuu-----uuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuuuuuuuuuuuuuuuuu

xxxxxx00uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu--11uuuu-uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu----uuuu----uuuu----uuuu----uuuuuuu--uuuuuuuuuuuuuuuuuuuuu---uuuuuuuuuuuuuuuuuuu-----uuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuuuuuuuuuuuuuuuuu

Rev.1.0047February17,2009

HT37A70/60/50/40/30/20RegisterWDTSADRXSPLXSPHADPCADPSASCRTMRAHTMRALRCOCCRTMRBHTMRBLRCOCRNote:

Reset(Power-on)00000111xxxxxxxx000000000000000000-0--00----1111-----000xxxxxxxxxxxxxxxx00001---xxxxxxxxxxxxxxxx------00

RESorLVRReset00000111xxxxxxxx000000000000000000-0--00----1111-----000xxxxxxxxxxxxxxxx00001---xxxxxxxxxxxxxxxx------00

WDTTime-out(NormalOperation)00000111xxxxxxxx000000000000000000-0--00----1111-----000xxxxxxxxxxxxxxxx00001---xxxxxxxxxxxxxxxx------00

WDTTime-out

(HALT)00000uuuuuuuuuuuuuuuuuuuuuuuuuuuuu-u--uu----uuuu-----uuuuuuuuuuuuuuuuuuuuuuuu---uuuuuuuuuuuuuuuu------uu

²u²standsforunchanged²x²standsforunknown

²-²standsforunimplemented

Rev.1.0048February17,2009

HT37A70/60/50/40/30/20Oscillator

Variousoscillatoroptionsoffertheuserawiderangeoffunctionsaccordingtotheirvariousapplicationrequire-ments.TwotypesofsystemclockscanbeselectedwhilevariousclocksourceoptionsfortheWatchdogTimerareprovidedformaximumflexibility.Alloscillatoroptionsareselectedthroughtheconfigurationoptions.Thetwomethodsofgeneratingthesystemclockare:

·Externalcrystal/resonatoroscillator·ExternalRCoscillator

withthecrystalorresonatormanufacturer¢sspecifica-tion.Theexternalparallelfeedbackresistor,Rp,isnor-mallynotrequiredbutinsomecasesmaybeneededtoassistwithoscillationstartup.

InternalCa,Cb,RfTypicalValues@5V,25°C

Ca7pF~9pF

Cb9pF~11pF

Rf300kW

OscillatorInternalComponentValues

ExternalRCOscillator

UsingtheexternalsystemRCoscillatorrequiresthataresistor,withavaluebetween82kWand180kW,iscon-nectedbetweenOSC1andVSS.Thegeneratedsystemclockdividedby8willbeprovidedonOSC2asanoutputwhichcanbeusedforexternalsynchronizationpur-poses.NotethatastheOSC2outputisanNMOSopen-draintype,apullhighresistorshouldbeconnectedifittobeusedtomonitortheinternalfrequency.Althoughthisisacosteffectiveoscillatorconfiguration,theoscilla-tionfrequencycanvarywithVDD,temperatureandpro-cessvariationsandisthereforenotsuitableforapplicationswheretimingiscriticalorwhereaccurateos-cillatorfrequenciesarerequired.Forthevalueoftheex-ternalresistor.Notethatitistheonlymicrocontrollerinternalcircuitrytogetherwiththeexternalresistor,thatdeterminethefrequencyoftheoscillator.Theexternalcapacitorshownonthediagramdoesnotinfluencethefrequencyofoscillation.

Oneofthesetwomethodsmustbeselectedusingtheconfigurationoptions.

MoreinformationregardingtheoscillatorislocatedinApplicationNoteHA0075EontheHoltekwebsite.ExternalCrystal/ResonatorOscillator

ThesimpleconnectionofacrystalacrossOSC1andOSC2willcreatethenecessaryphaseshiftandfeed-backforoscillation,andwillnormallynotrequireexter-nalcapacitors.However,forsomecrystalsandmostresonatortypes,toensureoscillationandaccuratefre-quencygeneration,itmaybenecessarytoaddtwosmallvalueexternalcapacitors,C1andC2.TheexactvaluesofC1andC2shouldbeselectedinconsultation

Crystal/ResonatorOscillator

ExternalRCOscillator

Rev.1.0049February17,2009

HT37A70/60/50/40/30/20WatchdogTimerOscillator

TheWDToscillatorisafullyself-containedfreerunningon-chipRCoscillatorwithatypicalperiodof65msat5Vrequiringnoexternalcomponents.Whenthedeviceen-tersthePowerDownMode,thesystemclockwillstoprunningbuttheWDToscillatorcontinuestofree-runandtokeepthewatchdogactive.However,topreservepowerincertainapplicationstheWDToscillatorcanbedisabledviaaconfigurationoption.

afixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcur-rentconsumption.Thisalsoappliestodeviceswhichhavedifferentpackagetypes,astheremaybeundonbedpins,whichmusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorscon-nected.Caremustalsobetakenwiththeloads,whichareconnectedtoI/Opins,whicharesetupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrentisdrawnorconnectedonlytoexternalcircuitsthatdonotdrawcurrent,suchasotherCMOSinputs.Alsonotethatadditionalstandbycurrentwillalsobere-quirediftheconfigurationoptionshaveenabledtheWatchdogTimerinternaloscillator.Wake-up

AfterthesystementersthePowerDownMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:

·Anexternalreset

·AnexternalfallingedgeonPortA·Asysteminterrupt·AWDToverflow

PowerDownModeandWake-up

PowerDownMode

AlloftheHoltekmicrocontrollershavetheabilitytoenteraPowerDownMode,alsoknownastheHALTModeorSleepMode.Whenthedeviceentersthismode,thenor-maloperatingcurrent,willbereducedtoanextremelylowstandbycurrentlevel.ThisoccursbecausewhenthedeviceentersthePowerDownMode,thesystemoscillatorisstoppedwhichreducesthepowerconsump-tiontoextremelylowlevels,however,asthedevicemaintainsitspresentinternalcondition,itcanbewokenupatalaterstageandcontinuerunning,withoutrequir-ingafullreset.Thisfeatureisextremelyimportantinap-plicationareaswheretheMCUmusthaveitspowersupplyconstantlymaintainedtokeepthedeviceinaknownconditionbutwherethepowersupplycapacityislimitedsuchasinbatteryapplications.EnteringthePowerDownMode

ThereisonlyonewayforthedevicetoenterthePowerDownModeandthatistoexecutethe²HALT²instruc-tionintheapplicationprogram.Whenthisinstructionisexecuted,thefollowingwilloccur:

·Thesystemoscillatorwillstoprunningandtheappli-

cationprogramwillstopatthe²HALT²instruction.

·TheDataMemorycontentsandregisterswillmaintain

Ifthesystemiswokenupbyanexternalreset,thede-vicewillexperienceafullsystemreset,however,ifthedeviceiswokenupbyaWDToverflow,aWatchdogTimerresetwillbeinitiated.Althoughbothofthesewake-upmethodswillinitiatearesetoperation,theac-tualsourceofthewake-upcanbedeterminedbyexam-iningtheTOandPDFflags.ThePDFflagisclearedbyasystempower-uporexecutingtheclearWatchdogTimerinstructionsandissetwhenexecutingthe²HALT²instruction.TheTOflagissetifaWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandStackPointer,theotherflagsremainintheiroriginalstatus.

EachpinonPortAcanbesetupviaanindividualconfig-urationoptiontopermitanegativetransitiononthepintowake-upthesystem.WhenaPortApinwake-upoc-curs,theprogramwillresumeexecutionattheinstruc-tionfollowingthe²HALT²instruction.

Ifthesystemiswokenupbyaninterrupt,thentwopossi-blesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexe-cutionattheinstructionfollowingthe²HALT²instruction.Inthissituation,theinterruptwhichwoke-upthedevicewillnotbeimmediatelyserviced,butwillratherbeser-vicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequestflagissetto²1²be-foreenteringthePowerDownMode,thewake-upfunc-tionoftherelatedinterruptwillbedisabled.

theirpresentcondition.

·TheWDTwillbeclearedandresumecountingifthe

WDTclocksourceisselectedtocomefromtheWDToscillator.TheWDTwillstopifitsclocksourceorigi-natesfromthesystemclock.

·TheI/Oportswillmaintaintheirpresentcondition.·Inthestatusregister,thePowerDownflag,PDF,will

besetandtheWatchdogtime-outflag,TO,willbecleared.

StandbyCurrentConsiderations

AsthemainreasonforenteringthePowerDownModeistokeepthecurrentconsumptionoftheMCUtoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-amps,thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesignerifthepowerconsumptionistobeminimized.Specialatten-tionmustbemadetotheI/Opinsonthedevice.Allhigh-impedanceinputpinsmustbeconnectedtoeither

Rev.1.0050February17,2009

HT37A70/60/50/40/30/20Nomatterwhatthesourceofthewake-upeventis,onceawake-upsituationoccurs,atimeperiodequalto1024systemclockperiodswillberequiredbeforenormalsys-temoperationresumes.However,ifthewake-uphasoriginatedduetoaninterrupt,theactualinterruptsub-routineexecutionwillbedelayedbyanadditionaloneormorecycles.Ifthewake-upresultsintheexecutionofthenextinstructionfollowingthe²HALT²instruction,thiswillbeexecutedimmediatelyafterthe1024systemclockperioddelayhasended.

sourceinsteadoftheinternalWDToscillator.Ifthein-structionclockisusedastheclocksource,itmustbenotedthatwhenthesystementersthePowerDownMode,asthesystemclockisstopped,thentheWDTclocksourcewillalsobestopped.ThereforetheWDTwillloseitsprotectingpurposes.Insuchcasesthesys-temcannotberestartedbytheWDTandcanonlybere-startedusingexternalsignals.Forsystemsthatoperateinnoisyenvironments,usingtheinternalWDToscillatoristhereforetherecommendedchoice.

Undernormalprogramoperation,aWDTtime-outwillinitialiseadeviceresetandsetthestatusbitTO.How-ever,ifthesystemisinthePowerDownMode,whenaWDTtime-outoccurs,onlytheProgramCounterandStackPointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWDTandtheWDTprescaler.Thefirstisanexternalhardwarereset,whichmeansalowlevelontheRESpin,thesecondisusingthewatchdogsoftwareinstructionsandthethirdisviaa²HALT²instruction.

TherearetwomethodsofusingsoftwareinstructionstocleartheWatchdogTimer,oneofwhichmustbechosenbyconfigurationoption.Thefirstoptionistousethesin-gle²CLRWDT²instructionwhilethesecondistousethetwocommands²CLRWDT1²and²CLRWDT2².Forthefirstoption,asimpleexecutionof²CLRWDT²willcleartheWDTwhileforthesecondoption,both²CLRWDT1²and²CLRWDT2²mustbothbeexecutedtosuccessfullycleartheWDT.Notethatforthissecondoption,if²CLRWDT1²isusedtocleartheWDT,succes-siveexecutionsofthisinstructionwillhavenoeffect,onlytheexecutionofa²CLRWDT2²instructionwillcleartheWDT.Similarly,afterthe²CLRWDT2²instruc-tionhasbeenexecuted,onlyasuccessive²CLRWDT1²instructioncancleartheWatchdogTimer.

WatchdogTimer

TheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlo-cations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.Itoperatesbyprovidingade-viceresetwhentheWDTcounteroverflows.TheWDTclockissuppliedbyoneoftwosourcesselectedbycon-figurationoption:itsownselfcontaineddedicatedinter-nalWDToscillatororfOSC/8.NotethatiftheWDTconfigurationoptionhasbeendisabled,thenanyin-structionrelatingtoitsoperationwillresultinnoopera-tion.

TheinternalWDToscillatorhasanapproximateperiodof65msatasupplyvoltageof5V.Ifselected,itisfirstdi-videdby256viaan8-stagecountertogiveanominalperiodof17ms.NotethatthisperiodcanvarywithVDD,temperatureandprocessvariations.ForlongerWDTtime-outperiodstheWDTprescalercanbeutilized.Bywritingtherequiredvaluetobits0,1and2oftheWDTSregister,knownasWS0,WS1andWS2,longertime-outperiodscanbeachieved.WithWS0,WS1andWS2allequalto1,thedivisionratiois1:128whichgivesamaxi-mumtime-outperiodofabout2.1s.

Aconfigurationoptioncanselecttheinstructionclock,whichisthesystemclockdividedby8,astheWDTclock

WatchdogTimerRegister

Rev.1.0051February17,2009

HT37A70/60/50/40/30/20WatchdogTimer

DigitaltoAnalogConverter(DACC)

ThetwoD/AconvertersofHT37A70/50/30are16-bithigh-resolutionwithexcellentfrequencyresponsecharacteristicsandgoodpowerconsumptionforstereoaudiooutput.

TheoneD/AconvertersofHT37A20is16-bithigh-resolutionwithexcellentfrequencyresponsecharacteristicsandgoodpowerconsumptionformonoaudiooutput.

1Dh1Eh1Fh

DACHighByteDACLowByteDACControl(DACC)

B15B7BP_R

D6B14B6

D5B13B5

D4B12B4

D3B11B3

D2B10B2

D1B9B1DAC

D0B8B0SELWR

SELACH1SELACH0AMP_MAMP_ENSELWL

Note:B15~B0isD/AconversionresultdatabitMSB~LSB.

DACC(1FH)Register

Note:

*SwitchMP1andMP2memorypointerbyBP_RHT37A20don¢tcontainbit2,bit3andbit4ofDACC

Rev.1.0052February17,2009

HT37A70/60/50/40/30/20TheIntegratedPowerAmp.

ThePowerAmp.isanintegratedclassABmonospeakerdrivercontainedinHT37A70/60/50/40/30.ItprovidespropertyofhighS/Nratio,highslewrate,lowdistortion,largeoutputvoltageswing,excellentpowersupplyripplerejection,lowpowerconsumption,lowstandbycurrentandpoweroffcontroletc.

SP0:AudioNegativeoutputSP1:AudioPositiveoutputOUTPRisingTime(tR)

WhenAMP_ENenable,thePowerAmp.needrisingtimetooutputfullyonOUTPpin.However,therisingtimedependson.

C1.(*TheC1connectswithVBIASandVss)

AudIn:Audioinput

VBIAS:Speakernon-invertinginputvoltagereference

CapacitortRVoltage2.2V3V415ms15ms15ms30ms30ms30ms90ms90ms90ms185ms185ms185ms0.1mF1mF4.7mF10mFForbatterybasedapplications,powerconsumptionisakeyissue,thereforetheamplifiershouldbeturnedoffwheninthestandbystate.Inordertoeliminateanyspeakersoundburstswhileturningtheamplifieron,theapplicationcircuit,whichwillincorporateacapacitancevalueofC1,shouldbeadjustedinaccordancewiththespeakersaudiofrequencyresponse.AgreatervalueofC1willimprovethenoiseburstwhileturningontheamplifier.Therecommendedoperationsequenceis:

TurnOn:audiosignalstandby(1/2VDD)®enableamplifier®waittRforamplifierready®audiooutputTurnOff:audiosignalfinished®disableamplifier®waittRforamplifieroff®audiosignaloff

IftheapplicationisnotpoweredbybatteriesandthereisnoproblemwithamplifierOn/Offissue,acapacitorvalueof0.1mFforC1isrecommended.HowtouseintegratedpowerAmp?

·Connectthe²InternalPowerAmpCircuit²,pleaserefertoApplicationCircuits.

·SetDACC.3toenableintegratedpoweramp.ClearDACC.3todisableintegratedpoweramp.·Usercancontrolitat²PowerAmpDisable²and²PowerAmpEnable²ofHT-MDS.

Rev.1.0053February17,2009

HT37A70/60/50/40/30/20MusicSynthesisController-MSC

CH0~CH7ChannelNumberSelection

Eachdeviceswithintegrated8channelsoutputisse-lectedby3bitsoptionandCHAN[2:0]isusedtodefinewhichchannelisselected.Whenthisregisteriswrittento,thewavetablesynthesizerwillautomaticallyoutputthededicatedPCMcode.Sothisregisterisalsousedasastartplayingkeyandithastobewrittentoafteralltheotherwavetablefunctionregistersarealreadydefined.ChangeParameterSelection

Thesetwobits,VMandFR,areusedtodefinewhichregisterwillbeupdatedonthisselectedchannel.Therearetwomodesthatcanbeselectedtoreducethepro-cessofsettingtheregister.Pleaserefertothestate-mentsofthefollowingtable:VM0011

FR0101

Function

Updatealltheparameter

OnlychangethefrequencyparameterOnlychangethevolumeparameterUnused

HT37A70/60containsST13~ST0isusedtodefinethestartaddressofeachPCMcodeandreadsthewave-formdatafromthislocation.

·HT37A70/60providesPCM12/8bitsource·PCM12Startaddressdefinition

·PCMcodehastobelocatedatamultipleof48(byte)·ST12~ST0=WA18~WA0/48·PCM8Startaddressdefinition

·PCMcodehastobelocatedatamultipleof32(byte)·ST13~ST0=WA18~WA0/32

HT37A50/40containsST12~ST0isusedtodefinethestartaddressofeachPCMcodeandreadsthewave-formdatafromthislocation.

·HT37A50/40providesPCM12/8bitsource·PCM12Startaddressdefinition

·PCMcodehastobelocatedatamultipleof48(byte)·ST11~ST0=WA17~WA0/48·PCM8Startaddressdefinition

·PCMcodehastobelocatedatamultipleof32(byte)·ST12~ST0=WA17~WA0/32

OutputFrequencyDefinition

ThedataonBL3~BL0andFR11~FR0areusedtode-finetheoutputspeedofthePCMfile,i.e.itcanbeusedtogeneratethetonescale.WhentheFR11~FR0is800HandBL3~BL0is6H,eachsampledataofthePCMcodewillbesentoutsequentially.

WhenthefOSCis11.059MHz,theformulaofatonefre-quencyis:

f/(16x8)FR11~FR0

fOUT=fRECORDxoscx(17-BL3~BL0)2SRwherefOUTistheoutputsignalfrequency,fRECORDandSR

isthefrequencyandsamplingrateonthesamplecode,respectively.

SoifavoicecodeofC3hasbeenrecordedwhichhasthefRECORDof261HzandtheSRof11025Hz,thetonefrequency(fOUT)ofG3:fOUT=98Hz.Canbeobtainedbyusingtheformula:IfFR=031handBL=7,couldget98Hz.

98Hz=261Hzx

FR11~FR086.4kHz

x(17-BL3~BL0)11.025kHz2HT37A30containsST11~ST0isusedtodefinethestartaddressofeachPCMcodeandreadsthewaveformdatafromthislocation.

·HT37A30providesPCM12/8bitsource·PCM12Startaddressdefinition

·PCMcodehastobelocatedatamultipleof48(byte)·ST10~ST0=WA16~WA0/48·PCM8Startaddressdefinition

·PCMcodehastobelocatedatamultipleof32(byte)·ST11~ST0=WA16~WA0/32

HT37A20containsST10~ST0isusedtodefinethestartaddressofeachPCMcodeandreadsthewaveformdatafromthislocation.

·HT37A20providesPCM12/8bitsource·PCM12Startaddressdefinition

·PCMcodehastobelocatedatamultipleof48(byte)·ST9~ST0=WA15~WA0/48·PCM8Startaddressdefinition

·PCMcodehastobelocatedatamultipleof32(byte)·ST10~ST0=WA15~WA0/32

BL3~BL0:rangefrom00h~0BhFR11~FR0:rangefrom000h~3FFhStartAddressDefinition

Eachdeviceprovidestwoaddresstypesforextendeduse,oneistheprogramROMaddresswhichisprogramcountercorrespondingwithBP1value,theotheristhestartaddressofthePCMcode.

Rev.1.0054February17,2009

HT37A70/60/50/40/30/20WaveformFormatDefinition

Eachdeviceacceptstwowaveformformatstoensureamoreeconomicaldataspace.WBSisusedtodefinethesampleformatofeachPCMcode.

WBS=0meansthesampleformatis8-bit(PCM8)WBS=1meansthesampleformatis12-bit(PCM12)The12-bitsampleformatallocateslocationtoeachsampledata.Pleaserefertothewaveformformatstate-mentasshownbelow.

RepeatNumberDefinition

Therepeatnumberisusedtodefinetheaddresswhichistherepeatpointofthesample.Whentherepeatnum-berisdefined,itwillbeoutputfromthestartcodetotheendcodeonceandalwaysoutputtherangebetweentherepeataddresstotheendcode(80H)untilthevol-umebecomeclose.TheRE14~RE0isusedtocalculatetherepeataddressofthePCMcode.TheprocessforsettingtheRE14~RE0istowritethe2¢scomplementoftherepeatlengthtoRE14~RE0,withthehighestcarryignored.TheHT37willgettherepeataddressbyaddingtheRE14~RE0totheaddressoftheendcode,thenjumptotheaddresstorepeatthisrange.VolumeControl

Eachdeviceprovidesthevolumecontrolindependently.ThevolumearecontrolledbyVR9~VR0respectively.Thechipprovides1024levelsofcontrollablevolume,the000Histhemaximumand3FFHistheminimumout-putvolume.ThePCMcodedefinitionEachdevicecanonlysolvethevoiceformatofthesigned8-bitor12-bitrawPCM.AndtheMCUwilltakethevoicecode80Hastheendcode.SoeachPCMcodesectionmustbeendedwiththeendcode80H.D7VMBL3FR7¾ST7WBSRE7A_R

D6FRBL2FR6¾ST6RE6¾¾

D5¾BL1FR5ST13ST5RE5VL9

D4¾BL0FR4ST12ST4RE4VL8

D3¾FR3ST11ST3RE3

D2CH2

D1CH1FR9FR1ST9ST1RE9RE1VR9

D0CH0FR8FR0ST8ST0RE8RE0VR8

Name20H21H22H23H24H25H26H27H28H29H2AH

Function

Channelnumberselection(CHAN)Frequencynumberhighbyte(FreqNH)Frequencynumberlowbyte(FreqNL)Startaddresshighbyte(AddrH)Startaddresslowbyte(AddrL)Repeatnumberhighbyte(RepH)Repeatnumberlowbyte(RepL)Controlregister(ENV)

FR11FR10

FR2ST10ST2RE2

RE14RE13RE12RE11RE10

ENV1ENV0

Leftvolumecontrol(LVC)Rightvolumecontrol(RVC)

VL7VR7

VL6VR6

VL5VR5

VL4VR4

VL3VR3

VL2VR2

VL1VR1

VL0VR0

WavetableRegisterMemoryMap(20h~2Ah)

ADPCM

AddressOffset

30H31H32H33H34H

RegisterName

ADRXSPLXSPHADPCADPS

R/WWWWR/WR

DefaultValuexxxxxxxx000000000000000000x0xx0000001111

Description

ADPCMDataRegister

Xn+SPInitialRegisterLowByteXn+SPInitialRegisterHighByteADPCMDecodercontrolregisterADPCMDecoderStatusRegister

HT-ADPCMDecoderRegisters

Rev.1.0055February17,2009

HT37A70/60/50/40/30/20ADPS(33H)-ADPCMStatusRegister

ExternalRCOscillationConverter

AnexternalRCoscillationconverterisimplementedincertaindevicesandisafunctionwhichallowstouchswitchfunctionstobeimplemented.Whenusedincon-junctionwiththeAnalogSwitchfunctionuptoeighttouchswitchescanbeimplemented.

ExternalRCOscillationConverterOperationTheRCoscillationconverteriscomposedoftwo16-bitcount-upprogrammabletimers.OneisTimerAandtheotheriscounterknownasTimerB.TheRCoscillationconverterisenabledwhentheRCObit,whichisbit1oftheRCOCRregister,issethigh.TheRCoscillationcon-verterwillthenbecomposedoffourregisters,TMRAL,TMRAH,TMRBLandTMRBH.TheTimerAclocksourcecomesfromthefSYSorfSYS/4,thechoiceofwhichisdeterminedbybitsintheRCOCCRregister.TheRCoscillationconverterTimerBclocksourcecomesfromanexternalRCoscillator.Astheoscillationfrequencyisdependentuponexternalcapacitanceandresistancevalues,itcanthereforebeusedtodetecttheincreasedcapacitanceofatouchswitchpad.

TherearesixregistersrelatedtotheRCoscillationcon-verter.Theseare,TMR2H,TMR2L,RCOCCR,TMR4H,TMR4LandRCOCR.Theinternaltimerclockisthein-putclocksourceforTMRAHandTMRAL,whiletheex-ternalRCoscillatoristheclocksourceinputtoTMRBHandTMRBL.TheOVBbit,whichisbit0oftheRCOCRregister,decideswhetherthetimerinterruptissourcedfromeithertheTimerAoverflowsorTimerBoverflow.Whenatimeroverflowoccurs,theRCOCFbitissetandanexternalRCoscillationconverterinterruptoccurs.WhentheRCoscillationconverterTimerAorTimerBoverflows,theRCOCONbitisautomaticallyresettozeroandstopscounting.

TheresistorandcapacitorformanoscillationcircuitandinputtoTMRBHandTMRBL.TheRCOM0,RCOM1andRCOM2bitsofRCOCCRdefinetheclocksourceofTimerA.

WhentheRCOCONbit,whichisbit4oftheRCOCCRregister,issethigh,TimerAandTimerBwillstartcount-inguntilTimerAorTimerBoverflows.NowthetimercounterwillgenerateaninterruptrequestflagwhichisbitRCOCF,bit5oftheINTCHregister.BothTimerAandTimerBwillthenstopcountingandtheRCOCONbitwillautomaticallyberesetto²0²atthesametime.NotethatiftheRCOCONbitishigh,theTMRAH,TMRAL,TMRBHandTMRBLregisterscannotbereadorwrittento.

RCOCCRRegister

Rev.1.0056February17,2009

HT37A70/60/50/40/30/20RCOCRRegister

ProgrammingConsiderations

Asthe16-bitTimershavebothlowbyteandhighbytetimerregisters,accessingtheseregistersiscarriedoutinaspecificway.Itmustbenotedthatwhenusingin-structionstopreloaddataintothelowbyteregisters,namelyTMRALorTMRAL,thedatawillonlybeplacedintoalowbytebufferandnotdirectlyintothelowbyteregister.Theactualtransferofthedataintothelowbyteregisterisonlycarriedoutwhenawritetoitsassociatedhighbyteregister,namelyTMRAHorTMRBH,isexe-cuted.However,usinginstructionstopreloaddataintothehighbytetimerregisterwillresultinthedatabeing

directlywrittentothehighbyteregister.Atthesametimethedatainthelowbytebufferwillbetransferredintoitsassociatedlowbyteregister.Forthisreason,whenpreloadingdataintothe16-bittimerregisters,thelowbyteshouldbewrittenfirst.Itmustalsobenotedthattoreadthecontentsofthelowbyteregister,areadtothehighbyteregistermustfirstbeexecutedtolatchthecontentsofthelowbytebufferintoitsassociatedlowbyteregister.Afterthishasbeendone,thelowbytereg-istercanbereadinthenormalway.Notethatreadingthelowbytetimerregisterwillonlyresultinreadingthepreviouslylatchedcontentsofthelowbytebufferandnottheactualcontentsofthelowbytetimerregister.

ProgramExample

ExternalRCoscillationconvertermodeexampleprogram-TimerAoverflow:clrRCOCCR

mova,00000010b;movRCOCR,aclrintch.5;mova,low(65536-1000);movtmral,a;mova,high(65536-1000)movtmrah,amova,00h;movtmrbl,amova,00hmovtmrbh,a

mova,00110000b;movRCOCCR,ap10:clrwdt

Snzintch.5;jmpp10

clrintch.5;;Programcontinue

EnableExternalRCoscillationmodeandsetTimerAoverflowClearExternalRCOscillationConverterinterruptrequestflagGivetimerAinitialvalue

TimerAcount1000timeandthenoverflowGivetimerBinitialvalue

TimerAclocksource=fSYS/4andtimeron

PollingExternalRCOscillationConverterinterruptrequestflagClearExternalRCOscillationConverterinterruptrequestflag

Rev.1.0057February17,2009

HT37A70/60/50/40/30/20AnalogSwitch

Thereare8analogswitchlinesinthemicrocontrollerforK0~K7forHT37A70/60/50/40/30,exceptHT37A20whichonlyhave4analogswitchlinesforK0~K3andtheAnalogSwitchcontrolregister,whichismappedtothedatamemory.AlloftheseAnalogSwitchlinescanbeusedfortouchkeyinputkeys.

AnalogSwitchControlRegister-ASCR

AnalogSwitch

Rev.1.0058February17,2009

HT37A70/60/50/40/30/20AnalogtoDigitalConverter

Theneedtointerfacetorealworldanalogsignalsisacommonrequirementformanyelectronicsystems.However,toproperlyprocessthesesignalsbyamicrocontroller,theymustfirstbeconvertedintodigitalsignalsbyA/Dconverters.ByintegratingtheA/Dcon-versionelectroniccircuitryintothemicrocontroller,theneedforexternalcomponentsisreducedsignificantlywiththecorrespondingfollow-onbenefitsoflowercostsandreducedcomponentspacerequirements.A/DOverview

HT37A70/60/50/40containsa8-channelanalogtodigi-talconverterwhichcandirectlyinterfacetoexternalan-alogsignals,suchasthatfromsensorsorothercontrolsignalsandconvertthesesignalsdirectlyintoeithera12-bitdigitalvalue.

DeviceHT37A70/60,HT37A50/40

InputConversion

InputPins

ChannelsBits

PB0~PB7

Inthefollowingtables,D0~D11aretheA/Dconversion

dataresultbits.RegisterADRLADRH

Bit7D3

Bit6D2

Bit5D1

Bit4D0D8

Bit3¾D7

Bit2¾D6

Bit1¾D5

Bit0¾D4

D11D10D9

A/DDataRegister

A/DConverterControlRegister-ADCR

TocontrolthefunctionandoperationoftheA/Dcon-verter,acontrolregisterknownasADCRisprovided.This8-bitregisterdefinesfunctionssuchastheselec-tionofwhichanalogchannelisconnectedtotheinternalA/Dconverter,whichpinsareusedasanaloginputsandwhichareusedasnormalI/OsaswellascontrollingthestartfunctionandmonitoringtheA/Dconverterendofconversionstatus.

OnesectionofthisregistercontainsthebitsACS2~ACS0whichdefinethechannelnumber.Aseachofthedevicescontainsonlyoneactualanalogtodigitalconvertercircuit,eachoftheindividual8analoginputsmustberoutedtotheconverter.ItisthefunctionoftheACS2~ACS0bitsintheADCRregistertodeter-minewhichanalogchannelisactuallyconnectedtotheinternalA/Dconverter.

TheADCRcontrolregisteralsocontainsthePCR2~PCR0bitswhichdeterminewhichpinsonPortAareusedasanaloginputsfortheA/DconverterandwhichpinsaretobeusedasnormalI/Opins.NotethatifthePCR2~PCR0bitsareallsettozero,thenallthePortBpinswillbesetupasnormalI/OsandtheinternalA/Dconvertercircuitrywillbepoweredofftoreducethepowerconsumption.

Thefollowingdiagramshowstheoverallinternalstruc-tureoftheA/Dconverter,togetherwithitsassociatedregisters.

A/DConverterDataRegisters-ADR,ADRL,ADRHHT37A70/60/50/40havea12-bitA/Dconverter,tworegistersarerequired,ahighbyteregister,knownasADRH,andalowbyteregister,knownasADRL.Aftertheconversionprocesstakesplace,theseregisterscanbedirectlyreadbythemicrocontrollertoobtainthedigi-tizedconversionvalue.HT37A70/60/50/40usetwoA/DConverterDataRegisters,notethatonlythehighbyteregisterADRHutilizesitsfull8-bitcontents.Thelowbyteregisterutilizesonly4bitofits8-bitcontentsasitcontainsonlythelower4bitofthe12-bitconvertedvalue.

A/DConverterStructure

Rev.1.0059February17,2009

HT37A70/60/50/40/30/20TheSTARTbitintheADCRregisterisusedtostartandresettheA/Dconverter.Whenthemicrocontrollersetsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversioncyclewillbeinitiated.WhentheSTARTbitisbroughtfromlowtohighbutnotlowagain,theEOCBbitintheADCRregisterwillbesethighandtheanalogtodigitalconverterwillbereset.ItistheSTARTbitthatisusedtocontroltheoverallon/offopera-tionoftheinternalanalogtodigitalconverter.

TheEOCBbitintheADCRregisterisusedtoindicatewhentheanalogtodigitalconversionprocessiscom-plete.Thisbitwillbeautomaticallyclearedtozerobythemicrocontrollerafteraconversioncyclehasended.Inaddition,thecorrespondingA/Dinterruptrequestflagwillbesetintheinterruptcontrolregister,andiftheinter-ruptsareenabled,anappropriateinternalinterruptsig-nalwillbegenerated.ThisA/DinternalinterruptsignalwilldirecttheprogramflowtotheassociatedA/Dinter-nalinterruptaddressforprocessing.IftheA/Dinternalinterruptisdisabled,themicrocontrollercanbeusedtopolltheEOCBbitintheADCRregistertocheckwhetherithasbeenclearedasanalternativemethodofdetect-ingtheendofanA/Dconversioncycle.

A/DConverterClockSourceRegister-ACSRTheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfOSC,isfirstdividedbyadivisionratio,thevalueofwhichisdeterminedbytheADCS1andADCS0bitsintheACSRregister.

AlthoughtheA/Dclocksourceisdeterminedbythesys-temclockfOSC,andbybitsADCS1andADCS0,therearesomelimitationsonthemaximumA/Dclocksourcespeedthatcanbeselected.Refertothefollowingtable.ACS300000000

ACS200001111

ACS100110011

ACS001010101

AnalogChannel

AN0AN1AN2AN3AN4AN5AN6AN7

ACSTable:A/DChannelSelectTable

ADCRRegister

ACSRRegister

Rev.1.0060February17,2009

HT37A70/60/50/40/30/20PCR200001111

PCR100110011

PCR001010101

7PB7PB7PB7PB7PB7PB7PB7AN7

6PB6PB6PB6PB6PB6PB6PB6AN6

5PB5PB5PB5PB5PB5AN5AN5AN5

4PB4PB4PB4PB4PB4AN4AN4AN4

3PB3PB3PB3PB3AN3AN3AN3AN3

2PB2PB2PB2AN2AN2AN2AN2AN2

1PB1PB1AN1AN1AN1AN1AN1AN1

0PB0AN0AN0AN0PB0AN0AN0AN0

PCRTable:PortA/DChannelConfigurationTable

A/DClockPeriod(tAD)

fOSC8MHz11.059MHz12MHz

ADCS1,ADCS0=00

(fOSC/4)

500ns362ns333ns

ADCS1,ADCS0=01

(fOSC/6)

750ns543ns500ns

A/DClockPeriodExamples

A/DInputPins

AlloftheA/Danaloginputpinsarepin-sharedwiththeI/OpinsonPortB.BitsPCR2~PCR0intheACSRregis-ters,notconfigurationoptions,determinewhethertheinputpinsaresetupasnormalPortBinput/outputpinsorwhethertheyaresetupasanaloginputs.Inthisway,pinscanbechangedunderprogramcontroltochangetheirfunctionfromnormalI/Ooperationtoanaloginputsandviceversa.Pull-highresistors,whicharesetupthroughconfigurationoptions,applytotheinputpinsonlywhentheyareusedasnormalI/Opins,ifsetupasA/Dinputsthepull-highresistorswillbeautomaticallydisconnected.NotethatitisnotnecessarytofirstsetuptheA/DpinasaninputinthePBCportcontrolregistertoenabletheA/Dinput,whenthePCR2~PCR0bitsen-ableanA/Dinput,thestatusoftheportcontrolregisterwillbeoverridden.

TheVDDpowersupplypinisusedastheA/Dconverterreferencevoltage,andassuchanaloginputsmustnotbeallowedtoexceedthisvalue.AppropriatemeasuresshouldalsobetakentoensurethattheVDDpinremainsasstableandnoisefreeaspossible.InitialisingtheA/DConverter

TheinternalA/Dconvertermustbeinitializedinaspecialway.EachtimethePortBA/Dchannelselectionbitsaremodifiedbytheprogram,theA/Dconvertermustbere-initialised.IftheA/Dconverterisnotinitializedafterthechannelselectionbitsarechanged,theEOCBflagmayhaveanundefinedvalue,whichmayproduceafalseendofconversionsignal.ToinitializetheA/DconverterafterRev.1.00

thechannelselectionbitshavechanged,then,withinatimeframeofonetoteninstructioncycles,theSTARTbitintheADCRregistermustfirstbesethighandthenim-mediatelyclearedtozero.ThiswillensurethattheEOCBflagiscorrectlysettoahighcondition.SummaryofA/DConversionSteps

ThefollowingsummarizestheindividualstepsthatshouldbeexecutedinordertoimplementanA/Dcon-versionprocess.

·Step1

ADCS1,ADCS0=10

(fOSC/8)

1ms723ns666ns

ADCS1,ADCS0=11

(fOSC/12)

1.5ms1.08ms1ms

SelecttherequiredA/DconversionclockbycorrectlyprogrammingbitsADCS1andADCS0intheACSRregister.

·Step2

SelectwhichchannelistobeconnectedtotheinternalA/DconverterbycorrectlyprogrammingtheACS2~ACS0bitswhicharealsocontainedintheADCRregister.

·Step3

SelectwhichpinsonPortBaretobeusedasA/Din-putsandconfigurethemasA/DinputpinsbycorrectlyprogrammingthePCR2~PCR0bitsintheADCRreg-ister.NotethatthisstepcanbecombinedwithStep2intoADCRregistersprogrammingoperation.

·Step4

TheanalogtodigitalconversionprocesscannowbeinitialisedbysettingtheSTARTbitintheADCRregis-terfrom²0²to²1²andthento²0²again.Notethatthisbitshouldhavebeenoriginallysetto²0².

·Step5

February17,2009

HT37A70/60/50/40/30/20Tocheckwhentheanalogtodigitalconversionpro-cessiscomplete,theEOCBbitintheADCRregistercanbepolled.Theconversionprocessiscompletewhenthisbitgoeslow.WhenthisoccurstheA/DdataregistersADRLandADRHcanbereadtoobtaintheconversionvalue.

Thefollowingtimingdiagramshowsgraphicallythevari-ousstagesinvolvedinananalogtodigitalconversionprocessanditsassociatedtiming.

A/DConversionTiming

ConfigurationOptions

ConfigurationoptionsrefertocertainoptionswithintheMCUthatareprogrammedintothedeviceduringtheprogram-mingprocess.Duringthedevelopmentprocess,theseoptionsareselectedusingtheHT-MDSsoftwaredevelopmenttools.Astheseoptionsareprogrammedintothedeviceusingthehardwareprogrammingtools,oncetheyareselectedtheycannotbechangedlaterastheapplicationsoftwarehasnocontrolovertheconfigurationoptions.Alloptionsmustbedefinedforpropersystemfunction,thedetailsofwhichareshowninthetable.No.1234567

WatchdogTimer:enableordisable

WatchdogTimerclocksource:T1(fOSC/8)orRCOSCCLRWDTinstructions:1or2instructionsPA0~PA7:wake-upenableordisable(bitoption)

PA,PB,PCandPD:pull-highenableordisable(portnumbersaredevicedependent)Systemoscillator:XtalModeorRCModeLVRfunction:enableordisableLVRfunction:3.3V/2.2V

SharePIN-PA5/INT:Enable(INT)/Disable(PA5)RtoFFunction:enableornormalI/O(PD)RtoF_AnalogSwitch:enableornormalI/O(PC)K0EnableandPC1~7K0~1EnableandPC2~7K0~2EnableandPC3~7K0~3EnableandPC4~7K0~4EnableandPC5~7K0~5EnableandPC6~7K0~6EnableandPC7K0~7Enable

Function

Rev.1.0062February17,2009

HT37A70/60/50/40/30/20ApplicationCircuits

Note:

IfuserhasusedinternalpowerAMPcircuit,needtoaddtwocapacitances(47mF,0.1mF)thatbeconnectedbe-tweenVDD_AMPandVSS.

HT37A20can¢tapplytheinternalpowerAMPcircuitapplicationbecauseitdon¢tintegratedPowerAmplifier.²*²Inapplicationcircuit,theRCHpinconnectinternalpoweramplifercircuitorexternalpoweramplifercircuitindividually.

Note:HT37A20onlyhasRCH.

Rev.1.0063February17,2009

HT37A70/60/50/40/30/20InstructionSet

Introduction

Centraltothesuccessfuloperationofanymicrocontrollerisitsinstructionset,whichisasetofpro-graminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontrollers,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofpro-grammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes,theyhavebeensubdividedintoseveralfunc-tionalgroupings.InstructionTiming

Mostinstructionsareimplementedwithinoneinstruc-tioncycle.Theexceptionstothisarebranch,call,orta-blereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan11.059MHzsys-temoscillator,mostinstructionswouldbeimplementedwithin0.723msandbranchorcallinstructionswouldbeimplementedwithin1ms.Althoughinstructionswhichre-quireonemorecycletoimplementaregenerallylimitedtotheJMP,CALL,RET,RETIandtablereadinstruc-tions,itisimportanttorealizethatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimple-ment.AsinstructionswhichchangethecontentsofthePCLwillimplyadirectjumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstruc-tionswouldbe²CLRPCL²or²MOVPCL,A².Forthecaseofskipinstructions,itmustbenotedthatifthere-sultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.MovingandTransferringData

Thetransferofdatawithinthemicrocontrollerprogramisoneofthemostfrequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimme-diatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsistoreceivedatafromtheinputportsandtransferdatatotheoutputports.ArithmeticOperations

Theabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddand

subtractinstructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbetakentoen-surecorrecthandlingofcarryandborrowdatawhenre-sultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.LogicalandRotateOperations

ThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontrollerinstructionset.Aswiththecaseofmostinstructionsinvolvingdatamanipulation,datamustpassthroughtheAccumulatorwhichmayinvolveadditionalprogrammingsteps.Inalllogicaldataoperations,thezeroflagmaybesetiftheresultoftheoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonpro-gramrequirements.RotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregisterintotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhererotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

BranchesandControlTransfer

ProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionortoasub-routineusingtheCALLinstruction.Theydifferinthesensethatinthecaseofasubroutinecall,theprogrammustreturntotheinstructionimmediatelywhenthesub-routinehasbeencarriedout.ThisisdonebyplacingareturninstructionRETinthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmadere-gardingtheconditionofacertaindatamemoryorindi-vidualbits.Dependingupontheconditions,theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.Theseinstructionsarethekeytodecisionmakingandbranchingwithinthepro-gramperhapsdeterminedbytheconditionofcertainin-putswitchesorbytheconditionofinternaldatabits.

Rev.1.00February17,2009

HT37A70/60/50/40/30/20BitOperations

TheabilitytoprovidesinglebitoperationsonDataMem-oryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeatureisespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe²SET[m].i²or²CLR[m].i²instructionsrespectively.Thefea-tureremovestheneedforprogrammerstofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writepro-cessistakencareofautomaticallywhenthesebitoper-ationinstructionsareused.TableReadOperations

Datastorageisnormallyimplementedbyusingregis-ters.However,whenworkingwithlargeamountsoffixeddata,thevolumeinvolvedoftenmakesitinconve-nienttostorethefixeddataintheDataMemory.Toover-comethisproblem,HoltekmicrocontrollersallowanareaofProgramMemorytobesetupasatablewheredatacanbedirectlystored.Asetofeasytouseinstruc-tionsprovidesthemeansbywhichthisfixeddatacanbereferencedandretrievedfromtheProgramMemory.

OtherOperations

Inadditiontotheabovefunctionalinstructions,arangeofotherinstructionsalsoexistsuchasthe²HALT²in-structionforPower-downoperationsandinstructionstocontroltheoperationoftheWatchdogTimerforreliableprogramoperationsunderextremeelectricorelectro-magneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.InstructionSetSummary

Thefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbecon-sultedasabasicinstructionreferenceusingthefollow-inglistedconventions.Tableconventions:x:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbits

addr:Programmemoryaddress

MnemonicArithmeticADDA,[m]ADDMA,[m]ADDA,xADCA,[m]ADCMA,[m]SUBA,xSUBA,[m]SUBMA,[m]SBCA,[m]SBCMA,[m]DAA[m]ANDA,[m]ORA,[m]XORA,[m]ANDMA,[m]ORMA,[m]XORMA,[m]ANDA,xORA,xXORA,xCPL[m]CPLA[m]INCA[m]INC[m]DECA[m]DEC[m]

Description

AddDataMemorytoACCAddACCtoDataMemoryAddimmediatedatatoACC

AddDataMemorytoACCwithCarryAddACCtoDatamemorywithCarrySubtractimmediatedatafromtheACCSubtractDataMemoryfromACC

SubtractDataMemoryfromACCwithresultinDataMemorySubtractDataMemoryfromACCwithCarry

SubtractDataMemoryfromACCwithCarry,resultinDataMemoryDecimaladjustACCforAdditionwithresultinDataMemoryLogicalANDDataMemorytoACCLogicalORDataMemorytoACCLogicalXORDataMemorytoACCLogicalANDACCtoDataMemoryLogicalORACCtoDataMemoryLogicalXORACCtoDataMemoryLogicalANDimmediateDatatoACCLogicalORimmediateDatatoACCLogicalXORimmediateDatatoACCComplementDataMemory

ComplementDataMemorywithresultinACCIncrementDataMemorywithresultinACCIncrementDataMemory

DecrementDataMemorywithresultinACCDecrementDataMemory

Cycles11Note11Note111Note111Note1Note111Note11Note1Note111Note1111

Note

FlagAffectedZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OV

ZZZZZZZZZZZZZZZ

LogicOperation

Increment&Decrement

11Note

Rev.1.0065February17,2009

HT37A70/60/50/40/30/20MnemonicRotateRRA[m]RR[m]RRCA[m]RRC[m]RLA[m]RL[m]RLCA[m]RLC[m]DataMoveMOVA,[m]MOV[m],AMOVA,xBitOperationCLR[m].iSET[m].iBranchJMPaddrSZ[m]SZA[m]SZ[m].iSNZ[m].iSIZ[m]SDZ[m]SIZA[m]SDZA[m]CALLaddrRETRETA,xRETITableReadTABRDC[m]TABRDL[m]MiscellaneousNOPCLR[m]SET[m]CLRWDTCLRWDT1CLRWDT2SWAP[m]SWAPA[m]HALTNote:

Nooperation

ClearDataMemorySetDataMemory

ClearWatchdogTimerPre-clearWatchdogTimerPre-clearWatchdogTimerSwapnibblesofDataMemory

SwapnibblesofDataMemorywithresultinACCEnterpowerdownmode

11Note1Note111Note111

NoneNoneNoneTO,PDFTO,PDFTO,PDFNoneNoneTO,PDF

Readtable(currentpage)toTBLHandDataMemoryReadtable(lastpage)toTBLHandDataMemory

2Note2Note

NoneNone

Jumpunconditionally

SkipifDataMemoryiszero

SkipifDataMemoryiszerowithdatamovementtoACCSkipifbitiofDataMemoryiszeroSkipifbitiofDataMemoryisnotzeroSkipifincrementDataMemoryiszeroSkipifdecrementDataMemoryiszero

SkipifincrementDataMemoryiszerowithresultinACCSkipifdecrementDataMemoryiszerowithresultinACCSubroutinecall

Returnfromsubroutine

ReturnfromsubroutineandloadimmediatedatatoACCReturnfrominterrupt

211note1Note1Note1Note1Note1Note1Note2222

Note

Description

RotateDataMemoryrightwithresultinACCRotateDataMemoryright

RotateDataMemoryrightthroughCarrywithresultinACCRotateDataMemoryrightthroughCarryRotateDataMemoryleftwithresultinACCRotateDataMemoryleft

RotateDataMemoryleftthroughCarrywithresultinACCRotateDataMemoryleftthroughCarryMoveDataMemorytoACCMoveACCtoDataMemoryMoveimmediatedatatoACCClearbitofDataMemorySetbitofDataMemory

Cycles11111

Note

FlagAffected

NoneNoneCCNoneNoneCCNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNone

Note

11Note1Note

1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.Forthe²CLRWDT1²and²CLRWDT2²instructionstheTOandPDFflagsmaybeaffectedbytheexecutionstatus.TheTOandPDFflagsareclearedafterboth²CLRWDT1²and²CLRWDT2²instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.

Rev.1.0066February17,2009

HT37A70/60/50/40/30/20InstructionDefinition

ADCA,[m]DescriptionOperationAffectedflag(s)ADCMA,[m]DescriptionOperationAffectedflag(s)ADDA,[m]DescriptionOperationAffectedflag(s)ADDA,xDescriptionOperationAffectedflag(s)ADDMA,[m]DescriptionOperationAffectedflag(s)ANDA,[m]DescriptionOperationAffectedflag(s)ANDA,xDescriptionOperationAffectedflag(s)ANDMA,[m]DescriptionOperationAffectedflag(s)Rev.1.00

AddDataMemorytoACCwithCarry

ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded.TheresultisstoredintheAccumulator.ACC¬ACC+[m]+COV,Z,AC,C

AddACCtoDataMemorywithCarry

ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded.TheresultisstoredinthespecifiedDataMemory.[m]¬ACC+[m]+COV,Z,AC,C

AddDataMemorytoACC

ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded.TheresultisstoredintheAccumulator.ACC¬ACC+[m]OV,Z,AC,C

AddimmediatedatatoACC

ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded.TheresultisstoredintheAccumulator.ACC¬ACC+xOV,Z,AC,C

AddACCtoDataMemory

ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded.TheresultisstoredinthespecifiedDataMemory.[m]¬ACC+[m]OV,Z,AC,C

LogicalANDDataMemorytoACC

DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalANDop-eration.TheresultisstoredintheAccumulator.ACC¬ACC²AND²[m]Z

LogicalANDimmediatedatatoACC

DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalANDoperation.TheresultisstoredintheAccumulator.ACC¬ACC²AND²xZ

LogicalANDACCtoDataMemory

DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalANDop-eration.TheresultisstoredintheDataMemory.[m]¬ACC²AND²[m]Z

February17,2009

HT37A70/60/50/40/30/20CALLaddrDescription

Subroutinecall

Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthenin-crementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothestack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthisnewaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruc-tion.

Stack¬ProgramCounter+1ProgramCounter¬addrNone

ClearDataMemory

EachbitofthespecifiedDataMemoryisclearedto0.[m]¬00HNone

ClearbitofDataMemory

BitiofthespecifiedDataMemoryisclearedto0.[m].i¬0None

ClearWatchdogTimer

TheTO,PDFflagsandtheWDTareallcleared.WDTclearedTO¬0PDF¬0TO,PDF

Pre-clearWatchdogTimer

TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunc-tionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohaveeffect.Re-petitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2willhavenoeffect.WDTclearedTO¬0PDF¬0TO,PDF

Pre-clearWatchdogTimer

TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunc-tionwithCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect.Re-petitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhavenoeffect.WDTclearedTO¬0PDF¬0TO,PDF

OperationAffectedflag(s)CLR[m]DescriptionOperationAffectedflag(s)CLR[m].iDescriptionOperationAffectedflag(s)CLRWDTDescriptionOperation

Affectedflag(s)CLRWDT1Description

Operation

Affectedflag(s)CLRWDT2Description

Operation

Affectedflag(s)

Rev.1.0068February17,2009

HT37A70/60/50/40/30/20CPL[m]DescriptionOperationAffectedflag(s)CPLA[m]Description

ComplementDataMemory

EachbitofthespecifiedDataMemoryislogicallycomplemented(1¢scomplement).Bitswhichpreviouslycontaineda1arechangedto0andviceversa.[m]¬[m]Z

ComplementDataMemorywithresultinACC

EachbitofthespecifiedDataMemoryislogicallycomplemented(1¢scomplement).Bitswhichpreviouslycontaineda1arechangedto0andviceversa.ThecomplementedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremainunchanged.ACC¬[m]Z

Decimal-AdjustACCforadditionwithresultinDataMemory

ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)valuere-sultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibbleremainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadd-ing00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflagmaybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan100,itallowsmultipleprecisiondecimaladdition.[m]¬ACC+00Hor[m]¬ACC+06Hor[m]¬ACC+60Hor[m]¬ACC+66HC

DecrementDataMemory

DatainthespecifiedDataMemoryisdecrementedby1.[m]¬[m]-1Z

DecrementDataMemorywithresultinACC

DatainthespecifiedDataMemoryisdecrementedby1.TheresultisstoredintheAccu-mulator.ThecontentsoftheDataMemoryremainunchanged.ACC¬[m]-1Z

Enterpowerdownmode

Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.ThecontentsoftheDataMemoryandregistersareretained.TheWDTandprescalerarecleared.ThepowerdownflagPDFissetandtheWDTtime-outflagTOiscleared.TO¬0PDF¬1TO,PDF

OperationAffectedflag(s)DAA[m]Description

Operation

Affectedflag(s)DEC[m]DescriptionOperationAffectedflag(s)DECA[m]DescriptionOperationAffectedflag(s)HALTDescription

OperationAffectedflag(s)

Rev.1.0069February17,2009

HT37A70/60/50/40/30/20INC[m]DescriptionOperationAffectedflag(s)INCA[m]DescriptionOperationAffectedflag(s)JMPaddrDescription

IncrementDataMemory

DatainthespecifiedDataMemoryisincrementedby1.[m]¬[m]+1Z

IncrementDataMemorywithresultinACC

DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumu-lator.ThecontentsoftheDataMemoryremainunchanged.ACC¬[m]+1Z

Jumpunconditionally

ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Programexecutionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummyinstructionwhilethenewaddressisloaded,itisatwocycleinstruction.ProgramCounter¬addrNone

MoveDataMemorytoACC

ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.ACC¬[m]None

MoveimmediatedatatoACC

TheimmediatedataspecifiedisloadedintotheAccumulator.ACC¬xNone

MoveACCtoDataMemory

ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.[m]¬ACCNoneNooperation

Nooperationisperformed.Executioncontinueswiththenextinstruction.NooperationNone

LogicalORDataMemorytoACC

DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalORoper-ation.TheresultisstoredintheAccumulator.ACC¬ACC²OR²[m]Z

OperationAffectedflag(s)MOVA,[m]DescriptionOperationAffectedflag(s)MOVA,xDescriptionOperationAffectedflag(s)MOV[m],ADescriptionOperationAffectedflag(s)NOPDescriptionOperationAffectedflag(s)ORA,[m]DescriptionOperationAffectedflag(s)

Rev.1.0070February17,2009

HT37A70/60/50/40/30/20ORA,xDescriptionOperationAffectedflag(s)ORMA,[m]DescriptionOperationAffectedflag(s)RETDescriptionOperationAffectedflag(s)RETA,xDescriptionOperationAffectedflag(s)RETIDescription

LogicalORimmediatedatatoACC

DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalORop-eration.TheresultisstoredintheAccumulator.ACC¬ACC²OR²xZ

LogicalORACCtoDataMemory

DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalORoper-ation.TheresultisstoredintheDataMemory.[m]¬ACC²OR²[m]Z

Returnfromsubroutine

TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesatthere-storedaddress.

ProgramCounter¬StackNone

ReturnfromsubroutineandloadimmediatedatatoACC

TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecifiedimmediatedata.Programexecutioncontinuesattherestoredaddress.ProgramCounter¬StackACC¬xNone

Returnfrominterrupt

TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbyset-tingtheEMIbit.EMIisthemasterinterruptglobalenablebit.IfaninterruptwaspendingwhentheRETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbe-forereturningtothemainprogram.ProgramCounter¬StackEMI¬1None

RotateDataMemoryleft

ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.

[m].(i+1)¬[m].i;(i=0~6)[m].0¬[m].7None

RotateDataMemoryleftwithresultinACC

ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryre-mainunchanged.

ACC.(i+1)¬[m].i;(i=0~6)ACC.0¬[m].7None

OperationAffectedflag(s)RL[m]DescriptionOperationAffectedflag(s)RLA[m]Description

OperationAffectedflag(s)

Rev.1.0071February17,2009

HT37A70/60/50/40/30/20RLC[m]DescriptionOperation

RotateDataMemoryleftthroughCarry

ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.[m].(i+1)¬[m].i;(i=0~6)[m].0¬CC¬[m].7C

RotateDataMemoryleftthroughCarrywithresultinACC

DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacestheCarrybitandtheoriginalcarryflagisrotatedintothebit0.TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremainunchanged.ACC.(i+1)¬[m].i;(i=0~6)ACC.0¬CC¬[m].7C

RotateDataMemoryright

ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.

[m].i¬[m].(i+1);(i=0~6)[m].7¬[m].0None

RotateDataMemoryrightwithresultinACC

DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0ro-tatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremainunchanged.ACC.i¬[m].(i+1);(i=0~6)ACC.7¬[m].0None

RotateDataMemoryrightthroughCarry

ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.[m].i¬[m].(i+1);(i=0~6)[m].7¬CC¬[m].0C

RotateDataMemoryrightthroughCarrywithresultinACC

DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0re-placestheCarrybitandtheoriginalcarryflagisrotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremainunchanged.ACC.i¬[m].(i+1);(i=0~6)ACC.7¬CC¬[m].0C

Affectedflag(s)RLCA[m]Description

Operation

Affectedflag(s)RR[m]DescriptionOperationAffectedflag(s)RRA[m]Description

OperationAffectedflag(s)RRC[m]DescriptionOperation

Affectedflag(s)RRCA[m]Description

Operation

Affectedflag(s)

Rev.1.0072February17,2009

HT37A70/60/50/40/30/20SBCA,[m]Description

SubtractDataMemoryfromACCwithCarry

ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagaresub-tractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.ACC¬ACC-[m]-COV,Z,AC,C

SubtractDataMemoryfromACCwithCarryandresultinDataMemory

ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagaresub-tractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthere-sultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.[m]¬ACC-[m]-COV,Z,AC,C

SkipifdecrementDataMemoryis0

ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.[m]¬[m]-1Skipif[m]=0None

SkipifdecrementDataMemoryiszerowithresultinACC

ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,thefollowinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecifiedDataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummyin-structionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.ACC¬[m]-1SkipifACC=0None

SetDataMemory

EachbitofthespecifiedDataMemoryissetto1.[m]¬FFHNone

SetbitofDataMemory

BitiofthespecifiedDataMemoryissetto1.[m].i¬1None

OperationAffectedflag(s)SBCMA,[m]Description

OperationAffectedflag(s)SDZ[m]Description

OperationAffectedflag(s)SDZA[m]Description

OperationAffectedflag(s)SET[m]DescriptionOperationAffectedflag(s)SET[m].iDescriptionOperationAffectedflag(s)

Rev.1.0073February17,2009

HT37A70/60/50/40/30/20SIZ[m]Description

SkipifincrementDataMemoryis0

ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.[m]¬[m]+1Skipif[m]=0None

SkipifincrementDataMemoryiszerowithresultinACC

ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,thefollowinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecifiedDataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummyin-structionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.ACC¬[m]+1SkipifACC=0None

SkipifbitiofDataMemoryisnot0

IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthisre-quirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Skipif[m].i¹0None

SubtractDataMemoryfromACC

ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.ACC¬ACC-[m]OV,Z,AC,C

SubtractDataMemoryfromACCwithresultinDataMemory

ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.TheresultisstoredintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.[m]¬ACC-[m]OV,Z,AC,C

SubtractimmediatedatafromACC

TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumu-lator.TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnega-tive,theCflagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.ACC¬ACC-xOV,Z,AC,C

OperationAffectedflag(s)SIZA[m]Description

OperationAffectedflag(s)SNZ[m].iDescription

OperationAffectedflag(s)SUBA,[m]Description

OperationAffectedflag(s)SUBMA,[m]Description

OperationAffectedflag(s)SUBA,xDescription

OperationAffectedflag(s)

Rev.1.0074February17,2009

HT37A70/60/50/40/30/20SWAP[m]DescriptionOperationAffectedflag(s)SWAPA[m]DescriptionOperationAffectedflag(s)SZ[m]Description

SwapnibblesofDataMemory

Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.[m].3~[m].0«[m].7~[m].4None

SwapnibblesofDataMemorywithresultinACC

Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.TheresultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.ACC.3~ACC.0¬[m].7~[m].4ACC.7~ACC.4¬[m].3~[m].0None

SkipifDataMemoryis0

IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruc-tion.

Skipif[m]=0None

SkipifDataMemoryis0withdatamovementtoACC

ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero,thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruc-tionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.ACC¬[m]Skipif[m]=0None

SkipifbitiofDataMemoryis0

IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisre-quirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Skipif[m].i=0None

Readtable(currentpage)toTBLHandDataMemory

Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.[m]¬programcode(lowbyte)TBLH¬programcode(highbyte)None

Readtable(lastpage)toTBLHandDataMemory

Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.[m]¬programcode(lowbyte)TBLH¬programcode(highbyte)None

OperationAffectedflag(s)SZA[m]Description

OperationAffectedflag(s)SZ[m].iDescription

OperationAffectedflag(s)TABRDC[m]DescriptionOperationAffectedflag(s)TABRDL[m]DescriptionOperationAffectedflag(s)

Rev.1.0075February17,2009

HT37A70/60/50/40/30/20XORA,[m]DescriptionOperationAffectedflag(s)XORMA,[m]DescriptionOperationAffectedflag(s)XORA,xDescriptionOperationAffectedflag(s)

LogicalXORDataMemorytoACC

DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXORop-eration.TheresultisstoredintheAccumulator.ACC¬ACC²XOR²[m]Z

LogicalXORACCtoDataMemory

DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXORop-eration.TheresultisstoredintheDataMemory.[m]¬ACC²XOR²[m]Z

LogicalXORimmediatedatatoACC

DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXORoperation.TheresultisstoredintheAccumulator.ACC¬ACC²XOR²xZ

Rev.1.0076February17,2009

HT37A70/60/50/40/30/20PackageInformation

20-pinSOP(300mil)OutlineDimensions

·MS-013

SymbolABCC¢DEFGHa

Dimensionsinmil

Min.39325612496¾¾41680°

Nom.¾¾¾¾¾50¾¾¾¾

Max.41930020512104¾1250138°

Rev.1.0077February17,2009

HT37A70/60/50/40/30/2028-pinSOP(300mil)OutlineDimensions

·MS-013

SymbolABCC¢DEFGHa

Dimensionsinmil

Min.39325612697¾¾41680°

Nom.¾¾¾¾¾50¾¾¾¾

Max.41930020713104¾1250138°

Rev.1.0078February17,2009

HT37A70/60/50/40/30/2048-pinSSOP(300mil)OutlineDimensions

SymbolABCC¢DEFGHa

Dimensionsinmil

Min.395291861385¾42540°

Nom.¾¾¾¾¾25¾¾¾¾

Max.4202991263799¾1035128°

Rev.1.0079February17,2009

HT37A70/60/50/40/30/20-pinQFP(14mm´20mm)OutlineDimensions

SymbolABCDEFGHIJKa

Dimensionsinmm

Min.18.813.924.819.9¾¾2.5¾¾1.150.10°

Nom.¾¾¾¾10.4¾¾0.1¾¾¾

Max.19.214.125.220.1¾¾3.13.4¾1.450.27°

Rev.1.0080February17,2009

HT37A70/60/50/40/30/2080-pinLQFP(10mm´10mm)OutlineDimensions

SymbolABCDEFGHIJKa

Dimensionsinmm

Min.11.99.911.99.9¾¾1.35¾¾0.450.10°

Nom.¾¾¾¾0.400.16¾¾0.1¾¾¾

Max.12.110.112.110.1¾¾1.451.6¾0.750.27°

Rev.1.0081February17,2009

HT37A70/60/50/40/30/20ProductTapeandReelSpecifications

ReelDimensions

SOP20W,SOP28W(300mil)

SymbolABCDT1T2

SSOP48W

SymbolABCDT1T2

Description

ReelOuterDiameterReelInnerDiameterSpindleHoleDiameterKeySlitWidth

SpaceBetweenFlangeReelThickness

Dimensionsinmm

330.0±1.0100.0±0.113.0+0.5/-0.22.0±0.532.2+0.3/-0.238.2±0.2

Description

ReelOuterDiameterReelInnerDiameterSpindleHoleDiameterKeySlitWidth

SpaceBetweenFlangeReelThickness

Dimensionsinmm

330.0±1.0100.0±1.513.0+0.5/-0.22.0±0.524.8+0.3/-0.230.2±0.2

Rev.1.0082February17,2009

HT37A70/60/50/40/30/20CarrierTapeDimensions

SOP20W

SymbolWPEFDD1P0P1A0B0K0tC

CavityPitchPerforationPosition

CavitytoPerforation(WidthDirection)PerforationDiameterCavityHoleDiameterPerforationPitch

CavitytoPerforation(LengthDirection)CavityLengthCavityWidthCavityDepth

CarrierTapeThicknessCoverTapeWidth

Description

CarrierTapeWidth

Dimensionsinmm

24.0+0.3/-0.112.0±0.11.75±0.1011.5±0.11.5+0.1/-0.01.50+0.25/-0.004.0±0.12.0±0.110.8±0.113.3±0.13.2±0.10.30±0.0521.3±0.1

SOP28W(300mil)

SymbolWPEFDD1P0P1A0B0K0tC

Rev.1.00

CavityPitchPerforationPosition

CavitytoPerforation(WidthDirection)PerforationDiameterCavityHoleDiameterPerforationPitch

CavitytoPerforation(LengthDirection)CavityLengthCavityWidthCavityDepth

CarrierTapeThicknessCoverTapeWidth

Description

CarrierTapeWidth

Dimensionsinmm

24.0±0.312.0±0.11.75±0.1011.5±0.11.5+0.1/-0.01.50+0.25/-0.004.0±0.12.0±0.110.85±0.1018.34±0.102.97±0.100.35±0.0121.3±0.1

February17,2009

HT37A70/60/50/40/30/20SSOP48W

SymbolWPEFDD1P0P1A0B0K1K2tC

Description

CarrierTapeWidthCavityPitchPerforationPosition

CavitytoPerforation(WidthDirection)PerforationDiameterCavityHoleDiameterPerforationPitch

CavitytoPerforation(LengthDirection)CavityLengthCavityWidthCavityDepthCavityDepth

CarrierTapeThicknessCoverTapeWidth

Dimensionsinmm

32.0±0.316.0±0.11.75±0.1014.2±0.12Min.1.50+0.25/-0.004.0±0.12.0±0.112.0±0.116.2±0.12.4±0.13.2±0.10.35±0.0525.5±0.1

Rev.1.0084February17,2009

HT37A70/60/50/40/30/20HoltekSemiconductorInc.(Headquarters)

No.3,CreationRd.II,SciencePark,Hsinchu,TaiwanTel:886-3-563-1999Fax:886-3-563-11http://www.holtek.com.tw

HoltekSemiconductorInc.(TaipeiSalesOffice)

4F-2,No.3-2,YuanQuSt.,NankangSoftwarePark,Taipei115,TaiwanTel:886-2-2655-7070Fax:886-2-2655-7373

Fax:886-2-2655-7383(Internationalsaleshotline)

HoltekSemiconductorInc.(ShanghaiSalesOffice)

GRoom,3Floor,No.1Building,No.2016Yi-ShanRoad,MinhangDistrict,Shanghai,China201103Tel:86-21-5422-4590Fax:86-21-5422-4705http://www.holtek.com.cn

HoltekSemiconductorInc.(ShenzhenSalesOffice)

5F,UnitA,ProductivityBuilding,GaoxinM2nd,MiddleZoneOfHigh-TechIndustrialPark,ShenZhen,China518057Tel:86-755-8616-9908,86-755-8616-9308Fax:86-755-8616-9722

HoltekSemiconductorInc.(BeijingSalesOffice)

Suite1721,JinyuTower,A129WestXuanWuMenStreet,XichengDistrict,Beijing,China100031Tel:86-10-61-0030,86-10-61-7751,86-10-61-7752Fax:86-10-61-0125

HoltekSemiconductorInc.(ChengduSalesOffice)

709,Building3,ChampagnePlaza,No.97DongdaStreet,Chengdu,Sichuan,China610016Tel:86-28-6653-6590Fax:86-28-6653-6591

HoltekSemiconductor(USA),Inc.(NorthAmericaSalesOffice)46729FremontBlvd.,Fremont,CA94538,USATel:1-510-252-9880Fax:1-510-252-9885http://www.holtek.com

CopyrightÓ2009byHOLTEKSEMICONDUCTORINC.

TheinformationappearinginthisDataSheetisbelievedtobeaccurateatthetimeofpublication.However,Holtekas-sumesnoresponsibilityarisingfromtheuseofthespecificationsdescribed.TheapplicationsmentionedhereinareusedsolelyforthepurposeofillustrationandHoltekmakesnowarrantyorrepresentationthatsuchapplicationswillbesuitablewithoutfurthermodification,norrecommendstheuseofitsproductsforapplicationthatmaypresentarisktohumanlifeduetomalfunctionorotherwise.Holtek¢sproductsarenotauthorizedforuseascriticalcomponentsinlifesupportdevicesorsystems.Holtekreservestherighttoalteritsproductswithoutpriornotification.Forthemostup-to-dateinformation,pleasevisitourwebsiteathttp://www.holtek.com.tw.

Rev.1.0085February17,2009

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