HCF41103B计数器

8-STAGE PRESETTABLE SYNCHRONOUS

8 BIT BINARY DOWN COUNTERS

s

s

ssss

ss

SYNCHRONOUS OR ASYNCHRONOUS PRESET

MEDIUM -SPEED OPERATION : fCL =3.6MHz (Typ.) at VDD = 10VCASCADABLE

QUIESCENT CURRENT SPECIF. UP TO 20V5V, 10V AND 15V PARAMETRIC RATINGSINPUT LEAKAGE CURRENT

II = 100nA (MAX) AT VDD = 18V TA = 25°C100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B \"STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES\"

DIPSOPORDER CODES

PACKAGEDIPSOP

TUBEHCF40103BEYHCF40103BM1

T & R

HCF40103M013TR

DESCRIPTION

HCF40103B is a monolithic integrated circuitfabricated in Metal Oxide Semiconductortechnology available in DIP and SOP packages. HCF40103B consists of an 8-stage synchronousdown counter with a single output that is activewhen the internal count is zero. This devicecontains a single 8-bit binary counter. It hascontrol inputs for enabling or disabling the clock,for clearing the counter to its maximum count, andfor presetting the counter either synchronously orasynchronously. All control inputs and theCARRY-OUT/ZERO DETECT output areactive-low logics. In normal operation, the counteris decremented by one count on each positivetransition of the CLOCK. Counting is inhibitedwhen the CARRY-IN/COUNTER ENABLE (CI/PIN CONNECTIONCE) input is high. The CARRY-OUT/ZERODETECT (CO/ZD) output goes low when thecount reaches zero if the CI/CE input is low, andremains low for one full clock period. When theSYNCHRONOUS PRESET ENABLE (SPE) inputis low, data at the JAM input is clocked into thecounter on the next positive clock transitionregardless of the state of the CI/CE input. Whenthe ASYNCHRONOUS PRESET ENABLE (APE)input is low, data at the JAM inputs isasynchronously forced into the counter regardlessof the state of the SPE, CI/CE, or CLOCK inputs.JAM inputs J0-J7 represent a single 8 bit binaryword. When the CLEAR (CLR) input is low, thecounter is asynchronously cleared to its maximumcount (25510) regardless of the state of any otherinput. The precedent relationship between controlinput is indicated in the truth table. If all control

September 20021/14

HCF40103B

inputs are high at the time of zero count, thecounters will jump to the maximum count, giving acounting sequence of 256 clock pulses long.IINPUT EQUIVALENT CIRCUIT

HCF40103B may be cascaded using the CI/CEinput and the CO/ZD output, in either asynchronous or ripple mode.PIN DESCRIPTION

PIN No123

4, 5, 6, 7, 10, 11, 12, 13

91415816

SYMBOLCLOCKCLEARCI/CEJ0 to J7APECO/ZDSPEVSSVDD

NAME AND FUNCTIONClock Input (LOW to HIGH edge triggered)Asynchronous Master Reset Input (Active Low)Terminal Enable InputJam Inputs

Asynchronous Preset Enable Inputs(Active Low)Terminal Count Output (Active Low)

Synchronous Preset

Enable Input (Active Low)Negative Supply VoltagePositive Supply Voltage

FUNCTIONAL DIAGRAM

TRUTH TABLES

CONTROL INPUTS

CLRHHHHL

APEHHHLX

SPEHHLXX

CI/CEHLXXX

PRESET MODE

ACTION

Inhibit CounterCount Down

Preset on Next Positive Clock TransitionPreset AsynchronouslyClear to Maximum Count

Synchronous

Asynchronous

X : Don’t Care

Clock connected to Clock input

Synchronous Operation : changes occur on negative to positive clock transitions.

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HCF40103B

LOGIC DIAGRAM

LOGIC DIAGRAM FOR FLIP-FLOPS, FF0-FF7

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HCF40103B

TIMING CHART

ABSOLUTE MAXIMUM RATINGS

SymbolVDDVIIIPDTopTstg

Supply VoltageDC Input VoltageDC Input Current

Power Dissipation per Package

Power Dissipation per Output TransistorOperating TemperatureStorage Temperature

Parameter

Value-0.5 to +22-0.5 to VDD + 0.5

± 10200100-55 to +125-65 to +150

UnitVVmAmWmW°C°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.

All voltage values are referred to VSS pin voltage.

RECOMMENDED OPERATING CONDITIONS

SymbolVDDVITop

Supply VoltageInput Voltage

Operating Temperature

Parameter

Value3 to 200 to VDD-55 to 125

UnitVV°C

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HCF40103B

DC SPECIFICATIONS

Test Condition

Symbol

Parameter

VI(V)0/50/100/150/200/50/100/155/010/015/0

0.5/4.51/91.5/13.54.5/0.59/113.5/1.52.54.69.513.50.40.51.5VO(V)

|IO|VDD(µA)(V)

5101520510155101551015510155510155101518

TA = 25°CMin.

Typ.0.040.040.040.08

4.959.9514.95

0.050.050.053.5711

1.534

-1.36-0.44-1.1-3.00.441.13.0

-3.2-1-2.6-6.812.66.8±10-55

-1.1-0.36-0.9-2.40.360.92.43.5711

1.534

-1.1-0.36-0.9-2.40.360.92.4

Max.51020100

4.959.9514.95

0.050.050.05

3.5711

1.534

Value-40 to 85°CMin.

Max.1503006003000

4.959.9514.95

0.050.050.05

-55 to 125°CMin.

Max.1503006003000

Unit

IL

Quiescent Current

µA

VOH

High Level Output Voltage

Low Level Output Voltage

High Level Input VoltageLow Level Input VoltageOutput Drive Current

VOL

VIH

VIL

IOH

IOL

Output Sink Current

Input Leakage Current

Input Capacitance

0/50/50/100/150/50/100/150/18

<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1

V

V

V

V

mA

mA

II

Any InputAny Input

±0.17.5

±1±1µApF

CI

The Noise Margin for both \"1\" and \"0\" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V

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HCF40103B

DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)

Test Condition

Symbol

Parameter

VDD (V)5101551015510155101551015510155101551015510155101551015

Min.

Value (*)Typ.3001309520090656503002003751801001005040150904016080501808060140705010040301.43..8

Max.600260190400180130130060040075036020020010080

nsUnit

tPHL tPLHPropagation Delay Time

Clock To OuttPHL tPLHPropagation Delay Time

Carry In/counter Enable To OutputtPHL tPLHPropagation Delay Time

Asynchronous Preset Enable To OutputtPHL tPLHPropagation Delay Time

Clear To OutputtTHL tTLHTransition Time

ns

ns

ns

ns

tW

Clock Pulse Width

tW

Clear Pulse Width

tW

APE Pulse Width

tsetup

SPE Setup Time

tsetup

JAM Setup Time

fCL

Maximum Clock Input Frequency

3001808032016010036016012028014010020080600.71.82.4

ns

ns

ns

ns

ns

MHz

(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.

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HCF40103B

TYPICAL APPLICATIONSDIVIDE BY \"N\" COUNTER

SYNCHRONOUS CASCADING

MICROPROCESSOR INTERRUPT TIMER SYNCHRONOUS CASCADING

MICROPROCESSOR INTERRUPT TIMER

* An Output spike (160ns at VDD = 5V) occurs whenever two or more devices are cascaded in the parallel clocked mode because the clock-to-carry out delay is greater than the carry-in-to-carry-out delay. This spike is eliminated by gating the output of the last device with the clock as shown.

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HCF40103B

TEST CIRCUIT

CL = 50pF or equivalent (includes jig and probe capacitance)RL = 200KΩ

RT = ZOUT of pulse generator (typically 50Ω)

WAVEFORM 1 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)

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HCF40103B

WAVEFORM 2 : PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle)

WAVEFORM 3 : PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle)

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HCF40103B

WAVEFORM 4 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)

WAVEFORM 5 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle)

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HCF40103B

WAVEFORM 6 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle)

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HCF40103BPlastic DIP-16 (0.25) MECHANICAL DATAmm.DIM.MIN.a1Bbb1DEee3FILZ3.31.278.52.5417.787.15.10.1300.0500.510.770.50.25200.3350.1000.7000.2800.2011.65TYPMAX.MIN.0.0200.0300.0200.0100.7870.065TYP.MAX.inchP001C12/14HCF40103BSO-16 MECHANICAL DATADIM.Aa1a2bb1Cc1DEee3FGLMS3.84.60.59.85.81.278.4.05.31.270.628˚ (max.)0.1490.1810.019106.20.350.190.545˚ (typ.)0.3850.2280.0500.3500.1570.2080.0500.0240.3930.2440.1mm.MIN.TYPMAX.1.750.21.650.460.250.0130.0070.0190.003MIN.inchTYP.MAX.0.0680.0070.00.0180.010PO13H13/14HCF40103B

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